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author | crupest <crupest@outlook.com> | 2021-12-03 19:34:17 +0800 |
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committer | crupest <crupest@outlook.com> | 2021-12-03 19:34:17 +0800 |
commit | 78ce0ddf1ab18e67d62b0f6b05ab010b0e4bb8c0 (patch) | |
tree | be61c6ba66ef7b9ac46e8ce5ecd69731f2c3143b /computer-organization-experiment/test_bench.vhdl | |
parent | 65b45752178e5c047d314d6e6852db5659c66cc9 (diff) | |
download | life-78ce0ddf1ab18e67d62b0f6b05ab010b0e4bb8c0.tar.gz life-78ce0ddf1ab18e67d62b0f6b05ab010b0e4bb8c0.tar.bz2 life-78ce0ddf1ab18e67d62b0f6b05ab010b0e4bb8c0.zip |
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Diffstat (limited to 'computer-organization-experiment/test_bench.vhdl')
-rw-r--r-- | computer-organization-experiment/test_bench.vhdl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/computer-organization-experiment/test_bench.vhdl b/computer-organization-experiment/test_bench.vhdl index 6e5e9e8..d2910d7 100644 --- a/computer-organization-experiment/test_bench.vhdl +++ b/computer-organization-experiment/test_bench.vhdl @@ -124,3 +124,23 @@ begin end loop; end process stimulus; end architecture test_shift_32; + + +architecture test_alu of test_bench is + signal A: std_logic_vector(31 downto 0) := "00000000000000000000000000000011"; + signal B: std_logic_vector(31 downto 0) := "00000000000000000000000000000011"; + signal S: std_logic_vector(31 downto 0); + signal ALUC: std_logic_vector(3 downto 0) := "0000"; + signal Z: std_logic; +begin + alu: entity work.alu(Behavioral) + port map (A, B, ALUC, S, Z); + stimulus: process is + begin + loop + wait for 5 ns; + ALUC <= ALUC + 1; + end loop; + + end process stimulus; +end architecture test_alu;
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