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author | Yuqian Yang <crupest@crupest.life> | 2025-02-12 15:55:21 +0800 |
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committer | Yuqian Yang <crupest@crupest.life> | 2025-02-12 15:55:21 +0800 |
commit | 10eb95869601e145b1d8bc909424777c25752d51 (patch) | |
tree | 49449a4076ded9bd937a51679318edbe2a532cae /works/life/computer-organization-experiment/adder_1.vhdl | |
parent | 29ba3e88b1a7425fe00af0005b8a8228103aa21c (diff) | |
parent | f8c10dd1fc55e60f35286475356e48c4f642eb63 (diff) | |
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Diffstat (limited to 'works/life/computer-organization-experiment/adder_1.vhdl')
-rw-r--r-- | works/life/computer-organization-experiment/adder_1.vhdl | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/works/life/computer-organization-experiment/adder_1.vhdl b/works/life/computer-organization-experiment/adder_1.vhdl new file mode 100644 index 0000000..625aae4 --- /dev/null +++ b/works/life/computer-organization-experiment/adder_1.vhdl @@ -0,0 +1,13 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity adder_1 is + port (A, B, CIN:in std_logic; S, COUT: out std_logic); +end adder_1; + +architecture behavior of adder_1 is +begin + S <= (A XOR B) XOR CIN; + COUT <= (A AND B) OR (B AND CIN) OR (CIN AND A); +end behavior; |