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authorYuqian Yang <crupest@crupest.life>2025-02-12 15:55:21 +0800
committerYuqian Yang <crupest@crupest.life>2025-02-12 15:55:21 +0800
commit1ecfd0ab7f1f511268fd6404dbc110c3c277b48c (patch)
tree49449a4076ded9bd937a51679318edbe2a532cae /works/life/computer-organization-experiment/adder_1.vhdl
parent55d8b025e8d6ea971e8ee5762c892405fedc316b (diff)
parentf8c10dd1fc55e60f35286475356e48c4f642eb63 (diff)
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+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity adder_1 is
+ port (A, B, CIN:in std_logic; S, COUT: out std_logic);
+end adder_1;
+
+architecture behavior of adder_1 is
+begin
+ S <= (A XOR B) XOR CIN;
+ COUT <= (A AND B) OR (B AND CIN) OR (CIN AND A);
+end behavior;