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authorYuqian Yang <crupest@crupest.life>2025-02-12 15:55:21 +0800
committerYuqian Yang <crupest@crupest.life>2025-02-12 15:55:21 +0800
commit10eb95869601e145b1d8bc909424777c25752d51 (patch)
tree49449a4076ded9bd937a51679318edbe2a532cae /works/life/computer-organization-experiment/counter_4.vhdl
parent29ba3e88b1a7425fe00af0005b8a8228103aa21c (diff)
parentf8c10dd1fc55e60f35286475356e48c4f642eb63 (diff)
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+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+ENTITY counter_4 IS
+ PORT (CLK:IN STD_LOGIC;
+ CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
+END counter_4;
+ARCHITECTURE behavior OF counter_4 IS
+BEGIN
+ PROCESS(CLK)
+ VARIABLE CQI:STD_LOGIC_VECTOR(3 DOWNTO 0) := B"0000";
+ BEGIN
+ IF CLK'EVENT AND CLK='1' THEN
+ CQI := CQI + 1;
+ END IF;
+ CQ<=CQI;
+ END PROCESS;
+END behavior;