diff options
Diffstat (limited to 'works/life')
5 files changed, 93 insertions, 1 deletions
diff --git a/works/life/computer-organization-experiment/Makefile b/works/life/computer-organization-experiment/Makefile index 1335118..96a830d 100644 --- a/works/life/computer-organization-experiment/Makefile +++ b/works/life/computer-organization-experiment/Makefile @@ -3,6 +3,15 @@ all: build/test_bench build: mkdir -p build +build/adder_1.o: build adder_1.vhdl + ghdl analyze --workdir=build -fsynopsys adder_1.vhdl + +build/adder_8.o: build adder_8.vhdl + ghdl analyze --workdir=build -fsynopsys adder_8.vhdl + +build/adder_32.o: build adder_32.vhdl + ghdl analyze --workdir=build -fsynopsys adder_32.vhdl + build/counter_4.o: build counter_4.vhdl ghdl analyze --workdir=build -fsynopsys counter_4.vhdl @@ -18,7 +27,7 @@ build/multiplexer_8_2.o: build multiplexer_8_2.vhdl build/multiplexer_32_2.o: build multiplexer_32_2.vhdl ghdl analyze --workdir=build -fsynopsys multiplexer_32_2.vhdl -build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o build/multiplexer_1_2.o build/multiplexer_8_2.o build/multiplexer_32_2.o +build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o build/multiplexer_1_2.o build/multiplexer_8_2.o build/multiplexer_32_2.o build/adder_1.o build/adder_8.o build/adder_32.o ghdl analyze --workdir=build -fsynopsys test_bench.vhdl build/test_bench: build/test_bench.o diff --git a/works/life/computer-organization-experiment/adder_1.vhdl b/works/life/computer-organization-experiment/adder_1.vhdl new file mode 100644 index 0000000..625aae4 --- /dev/null +++ b/works/life/computer-organization-experiment/adder_1.vhdl @@ -0,0 +1,13 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity adder_1 is + port (A, B, CIN:in std_logic; S, COUT: out std_logic); +end adder_1; + +architecture behavior of adder_1 is +begin + S <= (A XOR B) XOR CIN; + COUT <= (A AND B) OR (B AND CIN) OR (CIN AND A); +end behavior; diff --git a/works/life/computer-organization-experiment/adder_32.vhdl b/works/life/computer-organization-experiment/adder_32.vhdl new file mode 100644 index 0000000..f573f3f --- /dev/null +++ b/works/life/computer-organization-experiment/adder_32.vhdl @@ -0,0 +1,20 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity adder_32 is + port (A, B:in std_logic_vector(31 downto 0); CIN:in std_logic; S: out std_logic_vector(31 downto 0); COUT: out std_logic); +end adder_32; + +architecture behavior of adder_32 is + signal C : std_logic_vector(2 downto 0); +begin + c0: entity work.adder_8 + port map (A=>A(7 downto 0), B=>B(7 downto 0), CIN=>CIN, S=>S(7 downto 0), COUT=>C(0)); + c1: entity work.adder_8 + port map (A=>A(15 downto 8), B=>B(15 downto 8), CIN=>C(0), S=>S(15 downto 8), COUT=>C(1)); + c2: entity work.adder_8 + port map (A=>A(23 downto 16), B=>B(23 downto 16), CIN=>C(1), S=>S(23 downto 16), COUT=>C(2)); + c3: entity work.adder_8 + port map (A=>A(31 downto 24), B=>B(31 downto 24), CIN=>C(2), S=>S(31 downto 24), COUT=>COUT); +end behavior; diff --git a/works/life/computer-organization-experiment/adder_8.vhdl b/works/life/computer-organization-experiment/adder_8.vhdl new file mode 100644 index 0000000..840ee0d --- /dev/null +++ b/works/life/computer-organization-experiment/adder_8.vhdl @@ -0,0 +1,28 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity adder_8 is + port (A, B:in std_logic_vector(7 downto 0); CIN:in std_logic; S: out std_logic_vector(7 downto 0); COUT: out std_logic); +end adder_8; + +architecture behavior of adder_8 is + signal C : std_logic_vector(6 downto 0); +begin + b0: entity work.adder_1 + port map (A=>A(0), B=>B(0), CIN=>CIN, S=>S(0), COUT=>C(0)); + b1: entity work.adder_1 + port map (A=>A(1), B=>B(1), CIN=>C(0), S=>S(1), COUT=>C(1)); + b2: entity work.adder_1 + port map (A=>A(2), B=>B(2), CIN=>C(1), S=>S(2), COUT=>C(2)); + b3: entity work.adder_1 + port map (A=>A(3), B=>B(3), CIN=>C(2), S=>S(3), COUT=>C(3)); + b4: entity work.adder_1 + port map (A=>A(4), B=>B(4), CIN=>C(3), S=>S(4), COUT=>C(4)); + b5: entity work.adder_1 + port map (A=>A(5), B=>B(5), CIN=>C(4), S=>S(5), COUT=>C(5)); + b6: entity work.adder_1 + port map (A=>A(6), B=>B(6), CIN=>C(5), S=>S(6), COUT=>C(6)); + b7: entity work.adder_1 + port map (A=>A(7), B=>B(7), CIN=>C(6), S=>S(7), COUT=>COUT); +end behavior; diff --git a/works/life/computer-organization-experiment/test_bench.vhdl b/works/life/computer-organization-experiment/test_bench.vhdl index 756aa8d..64daf7f 100644 --- a/works/life/computer-organization-experiment/test_bench.vhdl +++ b/works/life/computer-organization-experiment/test_bench.vhdl @@ -62,3 +62,25 @@ begin end loop; end process stimulus; end architecture test_multiplexer_32_2; + +architecture test_adder_32 of test_bench is + signal A: std_logic_vector(31 downto 0) := B"00000000000000000000000000000000"; + signal B: std_logic_vector(31 downto 0) := B"00000000000000000000000000000000"; + signal CIN: std_logic; + signal S: std_logic_vector(31 downto 0); + signal COUT: std_logic; +begin + adder: entity work.adder_32(behavior) + port map (A, B, CIN, S, COUT); + stimulus: process is + begin + loop + A <= A + 1; + B <= B + 2; + CIN <= '0'; + wait for 5 ns; + CIN <= '1'; + wait for 5 ns; + end loop; + end process stimulus; +end architecture test_adder_32; |