From 6b99476d00173fedcb65fcedb418fcfb363f1e07 Mon Sep 17 00:00:00 2001 From: crupest Date: Tue, 9 Nov 2021 17:44:15 +0800 Subject: import(life): ... --- .../computer-organization-experiment/counter_4.vhdl | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 works/life/computer-organization-experiment/counter_4.vhdl (limited to 'works/life/computer-organization-experiment/counter_4.vhdl') diff --git a/works/life/computer-organization-experiment/counter_4.vhdl b/works/life/computer-organization-experiment/counter_4.vhdl new file mode 100644 index 0000000..23c1807 --- /dev/null +++ b/works/life/computer-organization-experiment/counter_4.vhdl @@ -0,0 +1,19 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +ENTITY counter_4 IS + PORT (CLK:IN STD_LOGIC; + CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); +END counter_4; +ARCHITECTURE behavior OF counter_4 IS +BEGIN + PROCESS(CLK) + VARIABLE CQI:STD_LOGIC_VECTOR(3 DOWNTO 0) := B"0000"; + BEGIN + IF CLK'EVENT AND CLK='1' THEN + CQI := CQI + 1; + END IF; + CQ<=CQI; + END PROCESS; +END behavior; -- cgit v1.2.3