From 6b99476d00173fedcb65fcedb418fcfb363f1e07 Mon Sep 17 00:00:00 2001 From: crupest Date: Tue, 9 Nov 2021 17:44:15 +0800 Subject: import(life): ... --- .../life/computer-organization-experiment/full_adder_1.vhdl | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 works/life/computer-organization-experiment/full_adder_1.vhdl (limited to 'works/life/computer-organization-experiment/full_adder_1.vhdl') diff --git a/works/life/computer-organization-experiment/full_adder_1.vhdl b/works/life/computer-organization-experiment/full_adder_1.vhdl new file mode 100644 index 0000000..9b269bf --- /dev/null +++ b/works/life/computer-organization-experiment/full_adder_1.vhdl @@ -0,0 +1,13 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity full_adder_1 is + port (A, B, CI:in std_logic; S, CO: out std_logic); +end full_adder_1; + +architecture behavior of full_adder_1 is +begin + S <= (A XOR B) XOR CI; + CO <= (A AND B) OR (B AND CI) OR (CI AND A); +end architecture; -- cgit v1.2.3