From e3fb643403ae71a38cba404e8d548d7a49cfdb88 Mon Sep 17 00:00:00 2001 From: crupest Date: Fri, 26 Nov 2021 21:24:20 +0800 Subject: import(life): Add computer organization 5. --- .../computer-organization-experiment/shift_32.vhdl | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 works/life/computer-organization-experiment/shift_32.vhdl (limited to 'works/life/computer-organization-experiment/shift_32.vhdl') diff --git a/works/life/computer-organization-experiment/shift_32.vhdl b/works/life/computer-organization-experiment/shift_32.vhdl new file mode 100644 index 0000000..5cb8425 --- /dev/null +++ b/works/life/computer-organization-experiment/shift_32.vhdl @@ -0,0 +1,23 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.numeric_std.all; + +entity shift_32 is + port( + D: in std_logic_vector(31 downto 0); + SA: in std_logic_vector(4 downto 0); + Right: in std_logic; + Arith: in std_logic; + SH: out std_logic_vector(31 downto 0) + ); +end entity; + +architecture behavioral of shift_32 is +begin + SH <= + std_logic_vector(signed(D) srl to_integer(unsigned(SA))) when Right = '1' and Arith = '0' + else std_logic_vector(signed(D) sll to_integer(unsigned(SA))) when Right = '0' and Arith = '0' + else std_logic_vector(signed(D) sra to_integer(unsigned(SA))) when Right = '1' and Arith = '1' + else std_logic_vector(signed(D) sla to_integer(unsigned(SA))) when Right = '0' and Arith = '1'; +end behavioral; -- cgit v1.2.3