From 6b99476d00173fedcb65fcedb418fcfb363f1e07 Mon Sep 17 00:00:00 2001 From: crupest Date: Tue, 9 Nov 2021 17:44:15 +0800 Subject: import(life): ... --- .../test_bench.vhdl | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 works/life/computer-organization-experiment/test_bench.vhdl (limited to 'works/life/computer-organization-experiment/test_bench.vhdl') diff --git a/works/life/computer-organization-experiment/test_bench.vhdl b/works/life/computer-organization-experiment/test_bench.vhdl new file mode 100644 index 0000000..be15df9 --- /dev/null +++ b/works/life/computer-organization-experiment/test_bench.vhdl @@ -0,0 +1,45 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity test_bench is +end test_bench; + +architecture test_counter_4 of test_bench is + signal CLK : STD_LOGIC; + signal CQ: STD_LOGIC_VECTOR(3 DOWNTO 0); +begin + counter: entity work.counter_4(behavior) + port map (CLK, CQ); + stimulus: process is + begin + for count_value in 0 to 2 ** 4 - 1 loop + if count_value mod 2 = 0 then + CLK <= '1'; + wait for 5 ns; + else + CLK <= '0'; + wait for 5 ns; + end if; + end loop; + end process stimulus; +end architecture test_counter_4; + + +architecture test_full_adder_1 of test_bench is + subtype v3 is std_logic_vector(2 downto 0); + signal I: v3 := B"000"; + signal S, CO : STD_LOGIC; +begin + adder: entity work.full_adder_1(behavior) + port map (I(2), I(1), I(0), S, CO); + stimulus: process is + variable ii : v3 := B"000"; + begin + loop + ii := ii + 1; + I <= ii; + wait for 5 ns; + end loop; + end process stimulus; +end architecture test_full_adder_1; -- cgit v1.2.3 From 31a285b083c36a2ed8e902b0f3325b8ccfa0bb37 Mon Sep 17 00:00:00 2001 From: crupest Date: Wed, 17 Nov 2021 16:59:04 +0800 Subject: import(life): ... --- .../life/computer-organization-experiment/Makefile | 15 ++++- .../computer-organization-experiment/hdl-prj.json | 12 ++++ .../multiplexer_1_2.vhdl | 20 +++++++ .../multiplexer_32_2.vhdl | 20 +++++++ .../multiplexer_8_2.vhdl | 20 +++++++ .../test_bench.vhdl | 69 ++++++++++++++-------- 6 files changed, 128 insertions(+), 28 deletions(-) create mode 100644 works/life/computer-organization-experiment/multiplexer_1_2.vhdl create mode 100644 works/life/computer-organization-experiment/multiplexer_32_2.vhdl create mode 100644 works/life/computer-organization-experiment/multiplexer_8_2.vhdl (limited to 'works/life/computer-organization-experiment/test_bench.vhdl') diff --git a/works/life/computer-organization-experiment/Makefile b/works/life/computer-organization-experiment/Makefile index d44613c..1335118 100644 --- a/works/life/computer-organization-experiment/Makefile +++ b/works/life/computer-organization-experiment/Makefile @@ -1,4 +1,4 @@ -all: build/counter_4.o build/test_bench.o build/full_adder_1.o build/test_bench +all: build/test_bench build: mkdir -p build @@ -9,10 +9,19 @@ build/counter_4.o: build counter_4.vhdl build/full_adder_1.o: build full_adder_1.vhdl ghdl analyze --workdir=build -fsynopsys full_adder_1.vhdl -build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o +build/multiplexer_1_2.o: build multiplexer_1_2.vhdl + ghdl analyze --workdir=build -fsynopsys multiplexer_1_2.vhdl + +build/multiplexer_8_2.o: build multiplexer_8_2.vhdl + ghdl analyze --workdir=build -fsynopsys multiplexer_8_2.vhdl + +build/multiplexer_32_2.o: build multiplexer_32_2.vhdl + ghdl analyze --workdir=build -fsynopsys multiplexer_32_2.vhdl + +build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o build/multiplexer_1_2.o build/multiplexer_8_2.o build/multiplexer_32_2.o ghdl analyze --workdir=build -fsynopsys test_bench.vhdl -build/test_bench: build/counter_4.o build/full_adder_1.o build/test_bench.o +build/test_bench: build/test_bench.o ghdl elaborate --workdir=build -fsynopsys -o build/test_bench test_bench .PHONY: all clean diff --git a/works/life/computer-organization-experiment/hdl-prj.json b/works/life/computer-organization-experiment/hdl-prj.json index 91428c1..1d997bb 100644 --- a/works/life/computer-organization-experiment/hdl-prj.json +++ b/works/life/computer-organization-experiment/hdl-prj.json @@ -17,6 +17,18 @@ { "file": "test_bench.vhdl", "language": "vhdl" + }, + { + "file": "multiplexer_1_2.vhdl", + "language": "vhdl" + }, + { + "file": "multiplexer_8_2.vhdl", + "language": "vhdl" + }, + { + "file": "multiplexer_32_2.vhdl", + "language": "vhdl" } ] } \ No newline at end of file diff --git a/works/life/computer-organization-experiment/multiplexer_1_2.vhdl b/works/life/computer-organization-experiment/multiplexer_1_2.vhdl new file mode 100644 index 0000000..5f73d6a --- /dev/null +++ b/works/life/computer-organization-experiment/multiplexer_1_2.vhdl @@ -0,0 +1,20 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity multiplexer_1_2 is + port (A0, A1, S : in std_logic; Y: out std_logic); +end multiplexer_1_2; + +architecture behaviour of multiplexer_1_2 is +begin + b: process is + begin + if S = '1' then + Y <= A1; + else + Y <= A0; + end if; + wait for 5 ns; + end process b; +end behaviour; diff --git a/works/life/computer-organization-experiment/multiplexer_32_2.vhdl b/works/life/computer-organization-experiment/multiplexer_32_2.vhdl new file mode 100644 index 0000000..917e0e3 --- /dev/null +++ b/works/life/computer-organization-experiment/multiplexer_32_2.vhdl @@ -0,0 +1,20 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity multiplexer_32_2 is + port (A0, A1 : in std_logic_vector(31 downto 0); S : in std_logic; Y : out std_logic_vector(31 downto 0)); +end multiplexer_32_2; + +architecture behaviour of multiplexer_32_2 is +begin + b: process is + begin + if S = '1' then + Y <= A1; + else + Y <= A0; + end if; + wait for 5 ns; + end process b; +end behaviour; diff --git a/works/life/computer-organization-experiment/multiplexer_8_2.vhdl b/works/life/computer-organization-experiment/multiplexer_8_2.vhdl new file mode 100644 index 0000000..5fffbf4 --- /dev/null +++ b/works/life/computer-organization-experiment/multiplexer_8_2.vhdl @@ -0,0 +1,20 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity multiplexer_8_2 is + port (A0, A1 : in std_logic_vector(7 downto 0); S : in std_logic; Y : out std_logic_vector(7 downto 0)); +end multiplexer_8_2; + +architecture behaviour of multiplexer_8_2 is +begin + b: process is + begin + if S = '1' then + Y <= A1; + else + Y <= A0; + end if; + wait for 5 ns; + end process b; +end behaviour; diff --git a/works/life/computer-organization-experiment/test_bench.vhdl b/works/life/computer-organization-experiment/test_bench.vhdl index be15df9..756aa8d 100644 --- a/works/life/computer-organization-experiment/test_bench.vhdl +++ b/works/life/computer-organization-experiment/test_bench.vhdl @@ -9,20 +9,20 @@ architecture test_counter_4 of test_bench is signal CLK : STD_LOGIC; signal CQ: STD_LOGIC_VECTOR(3 DOWNTO 0); begin - counter: entity work.counter_4(behavior) - port map (CLK, CQ); - stimulus: process is - begin - for count_value in 0 to 2 ** 4 - 1 loop - if count_value mod 2 = 0 then - CLK <= '1'; - wait for 5 ns; - else - CLK <= '0'; - wait for 5 ns; - end if; - end loop; - end process stimulus; + counter: entity work.counter_4(behavior) + port map (CLK, CQ); + stimulus: process is + begin + for count_value in 0 to 2 ** 4 - 1 loop + if count_value mod 2 = 0 then + CLK <= '1'; + wait for 5 ns; + else + CLK <= '0'; + wait for 5 ns; + end if; + end loop; + end process stimulus; end architecture test_counter_4; @@ -31,15 +31,34 @@ architecture test_full_adder_1 of test_bench is signal I: v3 := B"000"; signal S, CO : STD_LOGIC; begin - adder: entity work.full_adder_1(behavior) - port map (I(2), I(1), I(0), S, CO); - stimulus: process is - variable ii : v3 := B"000"; - begin - loop - ii := ii + 1; - I <= ii; - wait for 5 ns; - end loop; - end process stimulus; + adder: entity work.full_adder_1(behavior) + port map (I(2), I(1), I(0), S, CO); + stimulus: process is + variable ii : v3 := B"000"; + begin + loop + ii := ii + 1; + I <= ii; + wait for 5 ns; + end loop; + end process stimulus; end architecture test_full_adder_1; + +architecture test_multiplexer_32_2 of test_bench is + signal A0: std_logic_vector(31 downto 0) := B"11111111111111111111111111111111"; + signal A1: std_logic_vector(31 downto 0) := B"00000000000000000000000000000000"; + signal S: std_logic; + signal Y: std_logic_vector(31 downto 0); +begin + multiplexer: entity work.multiplexer_32_2(behaviour) + port map (A0, A1, S, Y); + stimulus: process is + begin + loop + S <= '0'; + wait for 5 ns; + S <= '1'; + wait for 5 ns; + end loop; + end process stimulus; +end architecture test_multiplexer_32_2; -- cgit v1.2.3 From 224d5fec9b9377faa4bf8d3da0e37f675ef5ea03 Mon Sep 17 00:00:00 2001 From: crupest Date: Tue, 23 Nov 2021 09:51:36 +0800 Subject: import(life): Add computer organization experiment 4. --- .../life/computer-organization-experiment/Makefile | 11 ++++++++- .../computer-organization-experiment/adder_1.vhdl | 13 ++++++++++ .../computer-organization-experiment/adder_32.vhdl | 20 ++++++++++++++++ .../computer-organization-experiment/adder_8.vhdl | 28 ++++++++++++++++++++++ .../test_bench.vhdl | 22 +++++++++++++++++ 5 files changed, 93 insertions(+), 1 deletion(-) create mode 100644 works/life/computer-organization-experiment/adder_1.vhdl create mode 100644 works/life/computer-organization-experiment/adder_32.vhdl create mode 100644 works/life/computer-organization-experiment/adder_8.vhdl (limited to 'works/life/computer-organization-experiment/test_bench.vhdl') diff --git a/works/life/computer-organization-experiment/Makefile b/works/life/computer-organization-experiment/Makefile index 1335118..96a830d 100644 --- a/works/life/computer-organization-experiment/Makefile +++ b/works/life/computer-organization-experiment/Makefile @@ -3,6 +3,15 @@ all: build/test_bench build: mkdir -p build +build/adder_1.o: build adder_1.vhdl + ghdl analyze --workdir=build -fsynopsys adder_1.vhdl + +build/adder_8.o: build adder_8.vhdl + ghdl analyze --workdir=build -fsynopsys adder_8.vhdl + +build/adder_32.o: build adder_32.vhdl + ghdl analyze --workdir=build -fsynopsys adder_32.vhdl + build/counter_4.o: build counter_4.vhdl ghdl analyze --workdir=build -fsynopsys counter_4.vhdl @@ -18,7 +27,7 @@ build/multiplexer_8_2.o: build multiplexer_8_2.vhdl build/multiplexer_32_2.o: build multiplexer_32_2.vhdl ghdl analyze --workdir=build -fsynopsys multiplexer_32_2.vhdl -build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o build/multiplexer_1_2.o build/multiplexer_8_2.o build/multiplexer_32_2.o +build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o build/multiplexer_1_2.o build/multiplexer_8_2.o build/multiplexer_32_2.o build/adder_1.o build/adder_8.o build/adder_32.o ghdl analyze --workdir=build -fsynopsys test_bench.vhdl build/test_bench: build/test_bench.o diff --git a/works/life/computer-organization-experiment/adder_1.vhdl b/works/life/computer-organization-experiment/adder_1.vhdl new file mode 100644 index 0000000..625aae4 --- /dev/null +++ b/works/life/computer-organization-experiment/adder_1.vhdl @@ -0,0 +1,13 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity adder_1 is + port (A, B, CIN:in std_logic; S, COUT: out std_logic); +end adder_1; + +architecture behavior of adder_1 is +begin + S <= (A XOR B) XOR CIN; + COUT <= (A AND B) OR (B AND CIN) OR (CIN AND A); +end behavior; diff --git a/works/life/computer-organization-experiment/adder_32.vhdl b/works/life/computer-organization-experiment/adder_32.vhdl new file mode 100644 index 0000000..f573f3f --- /dev/null +++ b/works/life/computer-organization-experiment/adder_32.vhdl @@ -0,0 +1,20 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity adder_32 is + port (A, B:in std_logic_vector(31 downto 0); CIN:in std_logic; S: out std_logic_vector(31 downto 0); COUT: out std_logic); +end adder_32; + +architecture behavior of adder_32 is + signal C : std_logic_vector(2 downto 0); +begin + c0: entity work.adder_8 + port map (A=>A(7 downto 0), B=>B(7 downto 0), CIN=>CIN, S=>S(7 downto 0), COUT=>C(0)); + c1: entity work.adder_8 + port map (A=>A(15 downto 8), B=>B(15 downto 8), CIN=>C(0), S=>S(15 downto 8), COUT=>C(1)); + c2: entity work.adder_8 + port map (A=>A(23 downto 16), B=>B(23 downto 16), CIN=>C(1), S=>S(23 downto 16), COUT=>C(2)); + c3: entity work.adder_8 + port map (A=>A(31 downto 24), B=>B(31 downto 24), CIN=>C(2), S=>S(31 downto 24), COUT=>COUT); +end behavior; diff --git a/works/life/computer-organization-experiment/adder_8.vhdl b/works/life/computer-organization-experiment/adder_8.vhdl new file mode 100644 index 0000000..840ee0d --- /dev/null +++ b/works/life/computer-organization-experiment/adder_8.vhdl @@ -0,0 +1,28 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity adder_8 is + port (A, B:in std_logic_vector(7 downto 0); CIN:in std_logic; S: out std_logic_vector(7 downto 0); COUT: out std_logic); +end adder_8; + +architecture behavior of adder_8 is + signal C : std_logic_vector(6 downto 0); +begin + b0: entity work.adder_1 + port map (A=>A(0), B=>B(0), CIN=>CIN, S=>S(0), COUT=>C(0)); + b1: entity work.adder_1 + port map (A=>A(1), B=>B(1), CIN=>C(0), S=>S(1), COUT=>C(1)); + b2: entity work.adder_1 + port map (A=>A(2), B=>B(2), CIN=>C(1), S=>S(2), COUT=>C(2)); + b3: entity work.adder_1 + port map (A=>A(3), B=>B(3), CIN=>C(2), S=>S(3), COUT=>C(3)); + b4: entity work.adder_1 + port map (A=>A(4), B=>B(4), CIN=>C(3), S=>S(4), COUT=>C(4)); + b5: entity work.adder_1 + port map (A=>A(5), B=>B(5), CIN=>C(4), S=>S(5), COUT=>C(5)); + b6: entity work.adder_1 + port map (A=>A(6), B=>B(6), CIN=>C(5), S=>S(6), COUT=>C(6)); + b7: entity work.adder_1 + port map (A=>A(7), B=>B(7), CIN=>C(6), S=>S(7), COUT=>COUT); +end behavior; diff --git a/works/life/computer-organization-experiment/test_bench.vhdl b/works/life/computer-organization-experiment/test_bench.vhdl index 756aa8d..64daf7f 100644 --- a/works/life/computer-organization-experiment/test_bench.vhdl +++ b/works/life/computer-organization-experiment/test_bench.vhdl @@ -62,3 +62,25 @@ begin end loop; end process stimulus; end architecture test_multiplexer_32_2; + +architecture test_adder_32 of test_bench is + signal A: std_logic_vector(31 downto 0) := B"00000000000000000000000000000000"; + signal B: std_logic_vector(31 downto 0) := B"00000000000000000000000000000000"; + signal CIN: std_logic; + signal S: std_logic_vector(31 downto 0); + signal COUT: std_logic; +begin + adder: entity work.adder_32(behavior) + port map (A, B, CIN, S, COUT); + stimulus: process is + begin + loop + A <= A + 1; + B <= B + 2; + CIN <= '0'; + wait for 5 ns; + CIN <= '1'; + wait for 5 ns; + end loop; + end process stimulus; +end architecture test_adder_32; -- cgit v1.2.3 From e3fb643403ae71a38cba404e8d548d7a49cfdb88 Mon Sep 17 00:00:00 2001 From: crupest Date: Fri, 26 Nov 2021 21:24:20 +0800 Subject: import(life): Add computer organization 5. --- .../life/computer-organization-experiment/Makefile | 25 ++++++++------ .../multiplexer_1_2.vhdl | 10 +----- .../multiplexer_32_2.vhdl | 10 +----- .../multiplexer_8_2.vhdl | 10 +----- .../computer-organization-experiment/shift_32.vhdl | 23 +++++++++++++ .../test_bench.vhdl | 40 ++++++++++++++++++++++ 6 files changed, 80 insertions(+), 38 deletions(-) create mode 100644 works/life/computer-organization-experiment/shift_32.vhdl (limited to 'works/life/computer-organization-experiment/test_bench.vhdl') diff --git a/works/life/computer-organization-experiment/Makefile b/works/life/computer-organization-experiment/Makefile index 96a830d..8777267 100644 --- a/works/life/computer-organization-experiment/Makefile +++ b/works/life/computer-organization-experiment/Makefile @@ -4,34 +4,37 @@ build: mkdir -p build build/adder_1.o: build adder_1.vhdl - ghdl analyze --workdir=build -fsynopsys adder_1.vhdl + ghdl analyze --std=08 --workdir=build -fsynopsys adder_1.vhdl build/adder_8.o: build adder_8.vhdl - ghdl analyze --workdir=build -fsynopsys adder_8.vhdl + ghdl analyze --std=08 --workdir=build -fsynopsys adder_8.vhdl build/adder_32.o: build adder_32.vhdl - ghdl analyze --workdir=build -fsynopsys adder_32.vhdl + ghdl analyze --std=08 --workdir=build -fsynopsys adder_32.vhdl build/counter_4.o: build counter_4.vhdl - ghdl analyze --workdir=build -fsynopsys counter_4.vhdl + ghdl analyze --std=08 --workdir=build -fsynopsys counter_4.vhdl build/full_adder_1.o: build full_adder_1.vhdl - ghdl analyze --workdir=build -fsynopsys full_adder_1.vhdl + ghdl analyze --std=08 --workdir=build -fsynopsys full_adder_1.vhdl build/multiplexer_1_2.o: build multiplexer_1_2.vhdl - ghdl analyze --workdir=build -fsynopsys multiplexer_1_2.vhdl + ghdl analyze --std=08 --workdir=build -fsynopsys multiplexer_1_2.vhdl build/multiplexer_8_2.o: build multiplexer_8_2.vhdl - ghdl analyze --workdir=build -fsynopsys multiplexer_8_2.vhdl + ghdl analyze --std=08 --workdir=build -fsynopsys multiplexer_8_2.vhdl build/multiplexer_32_2.o: build multiplexer_32_2.vhdl - ghdl analyze --workdir=build -fsynopsys multiplexer_32_2.vhdl + ghdl analyze --std=08 --workdir=build -fsynopsys multiplexer_32_2.vhdl -build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o build/multiplexer_1_2.o build/multiplexer_8_2.o build/multiplexer_32_2.o build/adder_1.o build/adder_8.o build/adder_32.o - ghdl analyze --workdir=build -fsynopsys test_bench.vhdl +build/shift_32.o: build shift_32.vhdl + ghdl analyze --std=08 --workdir=build -fsynopsys shift_32.vhdl + +build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o build/multiplexer_1_2.o build/multiplexer_8_2.o build/multiplexer_32_2.o build/adder_1.o build/adder_8.o build/adder_32.o build/shift_32.o + ghdl analyze --std=08 --workdir=build -fsynopsys test_bench.vhdl build/test_bench: build/test_bench.o - ghdl elaborate --workdir=build -fsynopsys -o build/test_bench test_bench + ghdl elaborate --std=08 --workdir=build -fsynopsys -o build/test_bench test_bench .PHONY: all clean diff --git a/works/life/computer-organization-experiment/multiplexer_1_2.vhdl b/works/life/computer-organization-experiment/multiplexer_1_2.vhdl index 3949e63..1fdeb0f 100644 --- a/works/life/computer-organization-experiment/multiplexer_1_2.vhdl +++ b/works/life/computer-organization-experiment/multiplexer_1_2.vhdl @@ -8,13 +8,5 @@ end multiplexer_1_2; architecture behaviour of multiplexer_1_2 is begin - b: process is - begin - if S = '1' then - Y <= A1; - else - Y <= A0; - end if; - wait for 1 ps; - end process b; + Y <= A0 when S = '0' else A1; end behaviour; diff --git a/works/life/computer-organization-experiment/multiplexer_32_2.vhdl b/works/life/computer-organization-experiment/multiplexer_32_2.vhdl index 563874d..1c7d626 100644 --- a/works/life/computer-organization-experiment/multiplexer_32_2.vhdl +++ b/works/life/computer-organization-experiment/multiplexer_32_2.vhdl @@ -8,13 +8,5 @@ end multiplexer_32_2; architecture behaviour of multiplexer_32_2 is begin - b: process is - begin - if S = '1' then - Y <= A1; - else - Y <= A0; - end if; - wait for 1 ps; - end process b; + Y <= A0 when S = '0' else A1; end behaviour; diff --git a/works/life/computer-organization-experiment/multiplexer_8_2.vhdl b/works/life/computer-organization-experiment/multiplexer_8_2.vhdl index d9e80f8..6be0bd2 100644 --- a/works/life/computer-organization-experiment/multiplexer_8_2.vhdl +++ b/works/life/computer-organization-experiment/multiplexer_8_2.vhdl @@ -8,13 +8,5 @@ end multiplexer_8_2; architecture behaviour of multiplexer_8_2 is begin - b: process is - begin - if S = '1' then - Y <= A1; - else - Y <= A0; - end if; - wait for 1 ps; - end process b; + Y <= A0 when S = '0' else A1; end behaviour; diff --git a/works/life/computer-organization-experiment/shift_32.vhdl b/works/life/computer-organization-experiment/shift_32.vhdl new file mode 100644 index 0000000..5cb8425 --- /dev/null +++ b/works/life/computer-organization-experiment/shift_32.vhdl @@ -0,0 +1,23 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.numeric_std.all; + +entity shift_32 is + port( + D: in std_logic_vector(31 downto 0); + SA: in std_logic_vector(4 downto 0); + Right: in std_logic; + Arith: in std_logic; + SH: out std_logic_vector(31 downto 0) + ); +end entity; + +architecture behavioral of shift_32 is +begin + SH <= + std_logic_vector(signed(D) srl to_integer(unsigned(SA))) when Right = '1' and Arith = '0' + else std_logic_vector(signed(D) sll to_integer(unsigned(SA))) when Right = '0' and Arith = '0' + else std_logic_vector(signed(D) sra to_integer(unsigned(SA))) when Right = '1' and Arith = '1' + else std_logic_vector(signed(D) sla to_integer(unsigned(SA))) when Right = '0' and Arith = '1'; +end behavioral; diff --git a/works/life/computer-organization-experiment/test_bench.vhdl b/works/life/computer-organization-experiment/test_bench.vhdl index 64daf7f..6e5e9e8 100644 --- a/works/life/computer-organization-experiment/test_bench.vhdl +++ b/works/life/computer-organization-experiment/test_bench.vhdl @@ -84,3 +84,43 @@ begin end loop; end process stimulus; end architecture test_adder_32; + +architecture test_shift_32 of test_bench is + signal D: std_logic_vector(31 downto 0) := B"00000000000000000000000000000011"; + signal SA: std_logic_vector(4 downto 0) := B"00000"; + signal Right: std_logic; + signal Arith: std_logic; + signal SH: std_logic_vector(31 downto 0); +begin + shift: entity work.shift_32(behavioral) + port map (D, SA, Right, Arith, SH); + stimulus: process is + begin + loop + D <= B"00000000000000000000000000000011" and D; + Right <= '0'; + Arith <= '0'; + wait for 5 ns; + Arith <= '1'; + wait for 5 ns; + Right <= '1'; + Arith <= '0'; + wait for 5 ns; + Arith <= '1'; + wait for 5 ns; + D <= B"10000000000000000000000000000000" or D; + Right <= '0'; + Arith <= '0'; + wait for 5 ns; + Arith <= '1'; + wait for 5 ns; + Right <= '1'; + Arith <= '0'; + wait for 5 ns; + Arith <= '1'; + wait for 5 ns; + + SA <= SA + 1; + end loop; + end process stimulus; +end architecture test_shift_32; -- cgit v1.2.3 From 44c58b206b910b15819a738c4a9995f8f840c039 Mon Sep 17 00:00:00 2001 From: crupest Date: Fri, 3 Dec 2021 19:34:17 +0800 Subject: import(life): ... --- .../life/computer-organization-experiment/Makefile | 5 ++++- .../life/computer-organization-experiment/alu.vhdl | 22 ++++++++++++++++++++++ .../test_bench.vhdl | 20 ++++++++++++++++++++ 3 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 works/life/computer-organization-experiment/alu.vhdl (limited to 'works/life/computer-organization-experiment/test_bench.vhdl') diff --git a/works/life/computer-organization-experiment/Makefile b/works/life/computer-organization-experiment/Makefile index 8777267..215a4e5 100644 --- a/works/life/computer-organization-experiment/Makefile +++ b/works/life/computer-organization-experiment/Makefile @@ -12,6 +12,9 @@ build/adder_8.o: build adder_8.vhdl build/adder_32.o: build adder_32.vhdl ghdl analyze --std=08 --workdir=build -fsynopsys adder_32.vhdl +build/alu.o: build alu.vhdl + ghdl analyze --std=08 --workdir=build -fsynopsys alu.vhdl + build/counter_4.o: build counter_4.vhdl ghdl analyze --std=08 --workdir=build -fsynopsys counter_4.vhdl @@ -30,7 +33,7 @@ build/multiplexer_32_2.o: build multiplexer_32_2.vhdl build/shift_32.o: build shift_32.vhdl ghdl analyze --std=08 --workdir=build -fsynopsys shift_32.vhdl -build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o build/multiplexer_1_2.o build/multiplexer_8_2.o build/multiplexer_32_2.o build/adder_1.o build/adder_8.o build/adder_32.o build/shift_32.o +build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o build/multiplexer_1_2.o build/multiplexer_8_2.o build/multiplexer_32_2.o build/adder_1.o build/adder_8.o build/adder_32.o build/shift_32.o build/alu.o ghdl analyze --std=08 --workdir=build -fsynopsys test_bench.vhdl build/test_bench: build/test_bench.o diff --git a/works/life/computer-organization-experiment/alu.vhdl b/works/life/computer-organization-experiment/alu.vhdl new file mode 100644 index 0000000..0bb743c --- /dev/null +++ b/works/life/computer-organization-experiment/alu.vhdl @@ -0,0 +1,22 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.numeric_std.all; + +entity alu is + port (A, B: in std_logic_vector(31 downto 0); ALUC: in std_logic_vector(3 downto 0); S: out std_logic_vector(31 downto 0); Z: out std_logic); +end entity; + +architecture Behavioral of alu is +begin + S <= A + B when ALUC(2 downto 0) = B"000" + else A and B when ALUC(2 downto 0) ?= B"001" + else A - B when ALUC(2 downto 0) ?= B"100" + else A or B when ALUC(2 downto 0) ?= B"101" + else A xor B when ALUC(2 downto 0) ?= B"010" + else std_logic_vector(signed(A) sll 16) and B"11111111111111110000000000000000" when ALUC(2 downto 0) ?= B"110" + else std_logic_vector(signed(A) sll to_integer(unsigned(B))) when ALUC ?= B"0011" + else std_logic_vector(signed(A) srl to_integer(unsigned(B))) when ALUC ?= B"0111" + else std_logic_vector(signed(A) sra to_integer(unsigned(B))) when ALUC ?= B"1111"; + Z <= S ?= "00000000000000000000000000000000"; +end architecture; diff --git a/works/life/computer-organization-experiment/test_bench.vhdl b/works/life/computer-organization-experiment/test_bench.vhdl index 6e5e9e8..d2910d7 100644 --- a/works/life/computer-organization-experiment/test_bench.vhdl +++ b/works/life/computer-organization-experiment/test_bench.vhdl @@ -124,3 +124,23 @@ begin end loop; end process stimulus; end architecture test_shift_32; + + +architecture test_alu of test_bench is + signal A: std_logic_vector(31 downto 0) := "00000000000000000000000000000011"; + signal B: std_logic_vector(31 downto 0) := "00000000000000000000000000000011"; + signal S: std_logic_vector(31 downto 0); + signal ALUC: std_logic_vector(3 downto 0) := "0000"; + signal Z: std_logic; +begin + alu: entity work.alu(Behavioral) + port map (A, B, ALUC, S, Z); + stimulus: process is + begin + loop + wait for 5 ns; + ALUC <= ALUC + 1; + end loop; + + end process stimulus; +end architecture test_alu; \ No newline at end of file -- cgit v1.2.3