From 8b5598a275b0b0bad61feb1d2afabd42c2e38daf Mon Sep 17 00:00:00 2001
From: crupest <crupest@outlook.com>
Date: Fri, 24 Dec 2021 19:36:03 +0800
Subject: import(life): ...

---
 .../life/computer-organization-experiment/alu.vhdl | 25 -------------------
 .../computer-organization-experiment/register.vhdl | 21 ----------------
 .../register_file.vhdl                             | 28 ----------------------
 3 files changed, 74 deletions(-)
 delete mode 100644 works/life/computer-organization-experiment/alu.vhdl
 delete mode 100644 works/life/computer-organization-experiment/register.vhdl
 delete mode 100644 works/life/computer-organization-experiment/register_file.vhdl

(limited to 'works/life')

diff --git a/works/life/computer-organization-experiment/alu.vhdl b/works/life/computer-organization-experiment/alu.vhdl
deleted file mode 100644
index 5eed3df..0000000
--- a/works/life/computer-organization-experiment/alu.vhdl
+++ /dev/null
@@ -1,25 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
-
-entity alu is
-    port (
-        A, B: in std_logic_vector(31 downto 0);
-        ALUC: in std_logic_vector(3 downto 0);
-        S: out std_logic_vector(31 downto 0);
-        Z: out std_logic);
-end entity;
-
-architecture Behavioral of alu is
-begin
-    S <= A + B when ALUC(2 downto 0) = B"000"
-         else A - B when ALUC(2 downto 0) ?= B"001"
-         else A and B when ALUC(2 downto 0) ?= B"100"
-         else A or B when ALUC(2 downto 0) ?= B"101"
-         else A xor B when ALUC(2 downto 0) ?= B"010"
-         else std_logic_vector(signed(A) sll 16) and H"FFFF0000" when ALUC(2 downto 0) ?= B"110"
-         else std_logic_vector(signed(A) sll to_integer(unsigned(B))) when ALUC ?= B"0011"
-         else std_logic_vector(signed(A) srl to_integer(unsigned(B))) when ALUC ?= B"0111"
-         else std_logic_vector(signed(A) sra to_integer(unsigned(B))) when ALUC ?= B"1111";
-    Z <= S ?= H"00000000";
-end architecture;
diff --git a/works/life/computer-organization-experiment/register.vhdl b/works/life/computer-organization-experiment/register.vhdl
deleted file mode 100644
index 8d24bd6..0000000
--- a/works/life/computer-organization-experiment/register.vhdl
+++ /dev/null
@@ -1,21 +0,0 @@
-library ieee;
-
-entity register is
-    port (
-        D : in std_logic_vector(31 downto 0);
-        CLK, EN, CLRN: in std_logic;
-        Q: out std_logic_vector(31 downto 0)
-    )
-end register;
-
-architecture Behavioral of register is
-begin
-    storage: process is
-    begin
-        if CLRN = '0' then
-            Q <= H"00000000";
-        elsif rising_edge(CLK) and EN = '1' then
-            Q <= D;
-        end if;
-    end process;
-end Behavioral;
diff --git a/works/life/computer-organization-experiment/register_file.vhdl b/works/life/computer-organization-experiment/register_file.vhdl
deleted file mode 100644
index ab1056f..0000000
--- a/works/life/computer-organization-experiment/register_file.vhdl
+++ /dev/null
@@ -1,28 +0,0 @@
-library ieee;
-
-entity register_file is
-    port (
-        CLK: in std_logic;
-        WRITE: in std_logic;
-        R1, R2, W: in std_logic_vector(4 downto 0);
-        WD: in std_logic_vector(31 downto 0);
-        RD1, RD2: out std_logic_vector(31 downto 0);
-    )
-end entity;
-
-architecture Behavioral of register_file is
-    type reg_file_type is array (0 to 31) of std_logic_vector(31 downto 0);
-    signal reg_file: reg_file_type := (others => '0');
-begin
-    process (CLK)
-    begin
-        if rising_edge(CLK) then
-        begin
-            if WRITE then
-                reg_file(W) <= WD;
-            end;
-            RD1 <= reg_file(R1);
-            RD2 <= reg_file(R2);
-        end;
-    end;
-end architecture;
-- 
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