$date
  Sat Dec 25 16:11:16 2021
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$scope module standard $end
$upscope $end
$scope module textio $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module numeric_std $end
$upscope $end
$scope module std_logic_arith $end
$upscope $end
$scope module std_logic_unsigned $end
$upscope $end
$scope module cru $end
$upscope $end
$scope module cpu_test_bench $end
$var reg 1 ! clk $end
$scope module clock $end
$var reg 1 " clk $end
$var reg 1 # v $end
$upscope $end
$scope module cpu $end
$var reg 1 $ clk $end
$var reg 32 % pc[31:0] $end
$var reg 32 & pc_to_write[31:0] $end
$var reg 32 ' ins[31:0] $end
$var reg 1 ( enable_mem $end
$var reg 1 ) write_mem $end
$var reg 32 * addr[31:0] $end
$var reg 32 + mem_w[31:0] $end
$var reg 32 , mem_r[31:0] $end
$var reg 1 - write_reg $end
$var reg 5 . r1[4:0] $end
$var reg 5 / r2[4:0] $end
$var reg 5 0 w[4:0] $end
$var reg 32 1 wd[31:0] $end
$var reg 32 2 rd1[31:0] $end
$var reg 32 3 rd2[31:0] $end
$var reg 32 4 a[31:0] $end
$var reg 32 5 b[31:0] $end
$var reg 4 6 aluc[3:0] $end
$var reg 32 7 s[31:0] $end
$var reg 1 8 z $end
$scope module pc_reg $end
$var reg 1 9 clk $end
$var reg 1 : enable $end
$var reg 32 ; w[31:0] $end
$var reg 32 < r[31:0] $end
$var reg 32 = v[31:0] $end
$upscope $end
$scope module reg $end
$var reg 1 > clk $end
$var reg 1 ? enable $end
$var reg 5 @ r1[4:0] $end
$var reg 5 A r2[4:0] $end
$var reg 5 B w[4:0] $end
$var reg 32 C wd[31:0] $end
$var reg 32 D rd1[31:0] $end
$var reg 32 E rd2[31:0] $end
$comment reg_file is not handled $end
$upscope $end
$scope module alu $end
$var reg 32 F a[31:0] $end
$var reg 32 G b[31:0] $end
$var reg 4 H aluc[3:0] $end
$var reg 32 I s[31:0] $end
$var reg 1 J z $end
$upscope $end
$scope module ram $end
$var reg 1 K clk $end
$var reg 32 L r[31:0] $end
$var reg 32 M w[31:0] $end
$var reg 32 N addr[31:0] $end
$var reg 1 O enable $end
$comment memory is not handled $end
$var reg 1 P v $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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