$date
  Sun Dec 26 07:20:30 2021
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$scope module standard $end
$upscope $end
$scope module textio $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module numeric_std $end
$upscope $end
$scope module std_logic_arith $end
$upscope $end
$scope module std_logic_unsigned $end
$upscope $end
$scope module cru $end
$upscope $end
$scope module cpu_test_bench $end
$var reg 1 ! clk $end
$scope module clock $end
$var reg 1 " clk $end
$var reg 1 # v $end
$upscope $end
$scope module cpu $end
$var reg 1 $ clk $end
$var reg 32 % pc[31:0] $end
$var reg 32 & pc_to_write[31:0] $end
$var reg 32 ' ins[31:0] $end
$var reg 32 ( mem_r_addr[31:0] $end
$var reg 32 ) mem_w_addr[31:0] $end
$var reg 32 * mem_r_data[31:0] $end
$var reg 32 + mem_w_data[31:0] $end
$var reg 1 , mem_read $end
$var reg 1 - mem_write $end
$var reg 1 . write_reg $end
$var reg 5 / r1[4:0] $end
$var reg 5 0 r2[4:0] $end
$var reg 5 1 w[4:0] $end
$var reg 32 2 wd[31:0] $end
$var reg 32 3 rd1[31:0] $end
$var reg 32 4 rd2[31:0] $end
$var reg 32 5 a[31:0] $end
$var reg 32 6 b[31:0] $end
$var reg 4 7 aluc[3:0] $end
$var reg 32 8 s[31:0] $end
$var reg 1 9 z $end
$scope module pc_reg $end
$var reg 1 : clk $end
$var reg 1 ; enable $end
$var reg 32 < w[31:0] $end
$var reg 32 = r[31:0] $end
$var reg 32 > v[31:0] $end
$upscope $end
$scope module reg $end
$var reg 1 ? clk $end
$var reg 1 @ enable $end
$var reg 5 A r1[4:0] $end
$var reg 5 B r2[4:0] $end
$var reg 5 C w[4:0] $end
$var reg 32 D wd[31:0] $end
$var reg 32 E rd1[31:0] $end
$var reg 32 F rd2[31:0] $end
$comment reg_file is not handled $end
$upscope $end
$scope module alu $end
$var reg 32 G a[31:0] $end
$var reg 32 H b[31:0] $end
$var reg 4 I aluc[3:0] $end
$var reg 32 J s[31:0] $end
$var reg 1 K z $end
$upscope $end
$scope module ram $end
$var reg 32 L r_data[31:0] $end
$var reg 32 M w_data[31:0] $end
$var reg 32 N r_addr[31:0] $end
$var reg 32 O w_addr[31:0] $end
$var reg 1 P read $end
$var reg 1 Q write $end
$comment memory is not handled $end
$var reg 1 R v $end
$var reg 1 S clk $end
$scope module clock $end
$var reg 1 T clk $end
$var reg 1 U v $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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