diff options
| author | Yann E. MORIN" <yann.morin.1998@anciens.enib.fr> | 2008-10-29 21:20:23 +0000 |
|---|---|---|
| committer | Yann E. MORIN" <yann.morin.1998@anciens.enib.fr> | 2008-10-29 21:20:23 +0000 |
| commit | d31396bc23bb78ed3d17ea3fdd3274ef7a8bdec1 (patch) | |
| tree | f23ebfdbc84d1f96fe367f468a5c0587c0347ca2 /patches/glibc | |
| parent | 2730c0b494ffb59cf78854d9f7925ddad559f3b3 (diff) | |
| download | crosstool-ng-d31396bc23bb78ed3d17ea3fdd3274ef7a8bdec1.tar.gz crosstool-ng-d31396bc23bb78ed3d17ea3fdd3274ef7a8bdec1.tar.bz2 crosstool-ng-d31396bc23bb78ed3d17ea3fdd3274ef7a8bdec1.zip | |
Finally enable the PPC-8xx memset workaround, by Nye Liu.
http://sourceware.org/ml/crossgcc/2008-10/msg00094.html
/trunk/scripts/build/libc/glibc.sh | 9 9 0 0 +
/trunk/patches/glibc/2.7/290-powerpc-8xx-CPU15-errata.patch | 22 19 3 0 +
/trunk/samples/powerpc-860-linux-gnu/crosstool.config | 344 344 0 0 +++++++++++++++++++
/trunk/samples/powerpc-860-linux-gnu/reported.by | 3 3 0 0 +
4 files changed, 375 insertions(+), 3 deletions(-)
Diffstat (limited to 'patches/glibc')
| -rw-r--r-- | patches/glibc/2.7/290-powerpc-8xx-CPU15-errata.patch | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/patches/glibc/2.7/290-powerpc-8xx-CPU15-errata.patch b/patches/glibc/2.7/290-powerpc-8xx-CPU15-errata.patch index 03cd4418..1d0643be 100644 --- a/patches/glibc/2.7/290-powerpc-8xx-CPU15-errata.patch +++ b/patches/glibc/2.7/290-powerpc-8xx-CPU15-errata.patch @@ -7,7 +7,7 @@ Quote: dcbX bug). The source of the problem is sysdeps/powerpc/power3/memset.S --- glibc-2.7/sysdeps/powerpc/powerpc32/memset.S 2007-03-26 13:09:07.000000000 -0700 -+++ glibc-2.7/sysdeps/powerpc/powerpc32/memset.S.new 2008-10-23 12:20:04.000000000 -0700 ++++ glibc-2.7/sysdeps/powerpc/powerpc32/memset.S.new 2008-10-23 20:28:52.000000000 -0700 @@ -112,11 +112,13 @@ clrrwi. rALIGN, rLEN, 5 mtcrf 0x01, rLEN /* 40th instruction from .align */ @@ -22,7 +22,23 @@ Quote: /* Store blocks of 32-bytes (256-bits) starting on a 32-byte boundary. Can't assume that rCHR is zero or that the cache line size is either -@@ -248,6 +250,7 @@ +@@ -158,6 +160,7 @@ + add rMEMP, rMEMP, rALIGN + b L(medium_tail2) /* 72nd instruction from .align */ + ++#ifndef BROKEN_PPC_8xx_CPU15 + .align 5 + nop + /* Clear cache lines of memory in 128-byte chunks. +@@ -191,6 +194,7 @@ + bdnz L(zloop) + beqlr cr5 + b L(medium_tail2) ++#endif /* ! BROKEN_PPC_8xx_CPU15 */ + + .align 5 + L(small): +@@ -248,6 +252,7 @@ stw rCHR, -8(rMEMP) blr @@ -30,7 +46,7 @@ Quote: L(checklinesize): #ifdef SHARED mflr rTMP -@@ -329,6 +332,7 @@ +@@ -329,6 +334,7 @@ L(handletail32): clrrwi. rALIGN, rLEN, 5 b L(nondcbz) |