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* kd: Include i386/irq.hSamuel Thibault2024-03-271-0/+1
| | | | to get unmask_irq declaration
* remove machine/machspl.h as it duplicates machine/spl.hLD2024-03-096-6/+6
| | | | Message-ID: <20240309140244.347835-2-luca@orpolo.org>
* Replace kernel header includes in include/mach/mach_types.h with forward ↵Flavio Cruz2024-02-121-0/+1
| | | | | | | | | | | | | | | declarations. I was trying to reuse TASK_NAME_SIZE in kern/thread.h but it was impossible because files included from kern/task.h end up requiring kern/thread.h (through percpu.h), creating a recursive dependency. With this change, mach_types.h only defines forward declarations and modules have to explicitly include the appropriate header file if they want to be able touch those structures. Most of the other includes are required because we no longer grab many different includes through mach_types.h. Message-ID: <20240212062634.1082207-1-flaviocruz@gmail.com>
* smp: Fix unable to enter kdb during bootDamien Zammit2024-02-112-2/+1
| | | | Message-ID: <20240211115958.1889648-1-damien@zamaudio.com>
* Fix build with APIC without SMPSamuel Thibault2024-02-101-1/+1
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* smp: Fix INIT/STARTUP IPI sequenceDamien Zammit2024-02-091-0/+5
| | | | | | TESTED: works in qemu TESTED: works hardware with AMD cpu Message-ID: <20240207050158.1640853-5-damien@zamaudio.com>
* SMP: Fix allocating the apboot pageSamuel Thibault2024-02-092-8/+9
| | | | | vm_page_grab_contig does not necessarily allocate at the beginning of the DMA segment, so rather allocate by hand very early.
* Add HPET timer for small accurate delaysDamien Zammit2024-02-083-8/+56
| | | | | | | TESTED: This works in qemu correctly TESTED: This works on an AMD board with ACPI v2.0 correctly Message-ID: <20240207050158.1640853-3-damien@zamaudio.com>
* separate lapic_enable from lapic_setupDamien Zammit2024-02-081-0/+1
| | | | | | | This initializes the lapic without turning on the IOAPIC interrupts during SMP init. Message-ID: <20240207050158.1640853-2-damien@zamaudio.com>
* apboot: avoid self-modifying codeSamuel Thibault2024-02-051-1/+6
| | | | | | self-modifying code is generally frowned upon, Intel largely says the support is model-dependent. We can as well just relocate from the C code like we did for the temporary gdt.
* smp: Remove hardcoded AP_BOOT_ADDRDamien Zammit2024-02-051-0/+18
| | | | | | | | | | | | | This took some time to figure out. Involves a hand-crafted 16 bit assembly instruction [1] because it requires an immediate for the memory address of far jump. This required self-modifying code to inject the next instruction, therefore I added a near jump to clear the instruction cache queue in case the pipeline cached the unmodified jump location. [1] Intel Architecture Software Developer's Manual, Volume 2: Instruction Set Reference Manual
* ACPI: Support XSDT (ACPI >= v2.0)Damien Zammit2024-02-013-89/+195
| | | | | | | | | This enables gnumach to additionally parse the XSDT table if the revision of ACPI is 2. TESTED: Still works on qemu (ACPI v1.0) TESTED: Works on a x86 board with XSDT (ACPI v2.0) Message-ID: <20240131021218.1335821-1-damien@zamaudio.com>
* model_dep: Fix serial console with APIC enabledDamien Zammit2024-02-011-5/+5
| | | | | | | Move cninit() further down so that IOAPIC has a chance to initialize before the com port interrupt is unmasked in the IOAPIC, fixing a fault and reboot. Message-ID: <20240131100210.1354522-1-damien@zamaudio.com>
* apic: Set up LAPICs in xAPIC modeDamien Zammit2024-01-301-1/+2
| | | | | | Clear flag in msr for xAPIC mode. Message-ID: <20240130080405.1304381-1-damien@zamaudio.com>
* Support up to two IOAPICs with up to 32 GSIs on eachDamien Zammit2024-01-293-6/+92
| | | | | | | Previously, only IOAPIC[0] was supported. Now this supports up to two IOAPICs. Message-ID: <20240129100652.1262126-1-damien@zamaudio.com>
* ioapic: Remove IMCR toggleDamien Zammit2024-01-271-6/+0
| | | | | | | | Since we are not using legacy MP tables but intending to use ACPI to configure interrupt routing, we can assume all boards have virtual wire mode, thus do not require setting of IMCR register. (This may fix crashes on machines that do not have IMCR registers). Message-ID: <20240124035138.1044855-2-damien@zamaudio.com>
* console: Fix baud rate on com ports, use 115200 default baud, 8 data bitsDamien Zammit2024-01-202-16/+5
| | | | | | | | TESTED: By booting gnumach off an HP T620 with console=com0 and receiving 115200 8N1 console on another machine connected via the serial port in minicom. Without this patch, part of the console is garbled by mismatching com params (9600 7N1). Message-ID: <20240119031214.691086-1-damien@zamaudio.com>
* Xen: fix buildSamuel Thibault2023-12-031-0/+2
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* Fix interrupt handlingDamien Zammit2023-10-031-15/+13
| | | | | | | | | | | | | | | | | | | | | | | | | Logic for interrupts: - interrupt.S raises spl (thus IF cleared) - interrupt.S EOI - interrupt.S calls the handler - for pure in-kernel handlers, they do whatever they want with IF cleared. - when a userland handler is registers, queue_intr masks the irq. - interrupt.S lowers spl with splx_cli, thus IF still cleared - iret, that sets IF - later on, userland acks the IRQ, that unmasks the irq The key to this change is that all interrupts, including IPIs, are treated the same way. Eg. the spl level is now raised before an IPI and restored after. Also, EOI is not needed inside irq_acknowledge. With this change and the experimental change not to dispatch threads direct to idle processors in the scheduler, I no longer observe kernel faults, but an occasional hang does occur. Message-Id: <20231002033906.124427-1-damien@zamaudio.com>
* com/lpr: Handle masking of interrupts in the driverDamien Zammit2023-10-012-8/+6
| | | | Message-Id: <20231001045755.95707-1-damien@zamaudio.com>
* kd: Handle masking of keyboard interrupt in the driverDamien Zammit2023-10-013-2/+8
| | | | Message-Id: <20231001045731.95682-1-damien@zamaudio.com>
* ioapic: Add simple locking for non-atomic accessesDamien Zammit2023-09-301-0/+9
| | | | Message-Id: <20230930063032.75232-3-damien@zamaudio.com>
* ioapic: Detect version of IOAPIC for correct EOI handlingDamien Zammit2023-09-301-1/+14
| | | | Message-Id: <20230930063032.75232-2-damien@zamaudio.com>
* boothdr: Fix initial gdtSamuel Thibault2023-09-241-1/+2
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* boothdr: Do not bother computing precise limitSamuel Thibault2023-09-241-2/+2
| | | | | Computing it would be complex, and this is a temporary descriptor anyway.
* boothdr: Drop spurious limit fieldSamuel Thibault2023-09-241-1/+1
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* boothdr: Also set up %gs for percpu accessSamuel Thibault2023-09-241-10/+59
| | | | So we can use it very early.
* percpu area using gs segmentDamien Zammit2023-09-241-0/+1
| | | | | | | | | | | | | | | This speeds up smp again, by storing the struct processor in a percpu area and avoiding an expensive cpu_number every call of current_processor(), as well as getting the cpu_number by an offset into the percpu area. Untested on 64 bit and work remains to use other percpu arrays. TESTED: (NCPUS=8) -smp 1 boots to login shell ~2x slower than uniprocessor TESTED: (NCPUS=8) -smp 2 boots to INIT but hangs there TESTED: (NCPUS=8) -smp 4 gets stuck seemingly within rumpdisk and hangs TESTED: (NCPUS=1) uniprocessor is a bit faster than normal Message-Id: <20230924103428.455966-3-damien@zamaudio.com>
* Fix crash at bootSamuel Thibault2023-08-282-0/+2
| | | | spl cannot be called before the clock is set up.
* page segments: Fix more dma32/directmap inversionsSamuel Thibault2023-08-211-3/+4
| | | | | We need to make sure segments are in addresses order, and avoid returning dma32 memory when it's not actually within directmap memory.
* immc: Add support for \r and \tSamuel Thibault2023-08-131-0/+8
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* IPI: Do not include support when NCPUS=1Samuel Thibault2023-08-132-0/+6
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* IPI: Rework irq names and fix x86_64 buildSamuel Thibault2023-08-133-7/+7
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* i386/x86_64: Add remote AST via IPI mechanismDamien Zammit2023-08-133-0/+15
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* tty: Convert t_lock to using simple_lock_irqSamuel Thibault2023-08-121-10/+7
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* model_dep: drop duplicate declarationSamuel Thibault2023-08-121-4/+0
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* Acknowledge IRQ *before* calling the handlerSamuel Thibault2023-08-101-25/+27
| | | | | | | | | | | | 5da1aea7ab3c ("Acknoledge interrupt after handler call") moved the IRQ ack to after calling the handler because of overflows. But that was because the interrupts were getting enabled at some point. Now that all spl levels above 0 just disable interrupts, once we have called spl7 we are safe until splx_cli is called (and even that doesn't release interrupts, only the eventual iret will). And if the handler triggers another IRQ, it will be lost, so we do want to ack the IRQ before handling it.
* Fix missing DMA32 limitSamuel Thibault2023-08-091-0/+19
| | | | | | | | | | | Rumpdisk needs to allocate dma32 memory areas, so we do always need this limit. The non-Xen x86_64 case had a typo, and the 32bit PAE case didn't have the DMA32 limit. Also, we have to cope with VM_PAGE_DMA32_LIMIT being either above or below VM_PAGE_DIRECTMAP_LIMIT depending on the cases.
* interrupt.S: No nested interrupts during IPIs && more x86_64 smp supportDamien Zammit2023-08-061-0/+1
| | | | Message-Id: <20230805154843.2003098-1-damien@zamaudio.com>
* cpu_number: Look up cpu kernel_id via lookup tableDamien Zammit2023-08-051-0/+2
| | | | | | | | | | This speeds up smp slightly by reducing the cpu_number() complexity to have no branching, just a look up table. It also addresses the problem that CPU_NUMBER was only using raw apic_id as an approximation of the kernel_id. Other improvements were to remove unnecessary checks now that the lookup table always resolves to a valid value. Message-Id: <20230805074945.1983707-1-damien@zamaudio.com>
* x86_64: fix APIC initializationLuca Dariz2023-05-211-4/+4
| | | | | | | * i386/i386at/acpi_parse_apic.c: use vm_offset_t instead of uint32_t for vm addresses * x86_64/Makefrag.am: support --enable-apic Message-Id: <20230521204918.492957-1-luca@orpolo.org>
* Do not expose CPU_TYPE_X86_64 when running 32bit userlandSamuel Thibault2023-05-111-1/+1
| | | | So that userland's uname -m still reports i686-AT386.
* x86_64: Add CPU_TYPE_X86_64 CPU typeSamuel Thibault2023-05-061-0/+4
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* Fix Xen buildSamuel Thibault2023-04-111-0/+2
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* ioapic: Timer calibrated in 10 mach ticksDamien Zammit2023-03-111-5/+4
| | | | | | | | hz variable is the number of mach ticks in 1 second. We want to know how many lapic ticks in 1 mach tick. Therefore, we set a timer for 10 mach ticks and divide the lapic stopwatch counter value by 10. Message-Id: <20230311072937.450161-1-damien@zamaudio.com>
* lapic timer: Calibrate via mach timer not PITDamien Zammit2023-03-072-37/+52
| | | | | | | | | | | Previously the lapic timer was calibrated by one-shot PIT timer2. This method can be buggy and generally unused in emulation environments. This patch reworks the timer calibration to use a mach timer based on regular PIT interrupts to remapped IOAPIC pin. This also changes the primary clock source to use PIT timer0 remapped to an IOAPIC pin when APIC mode is enabled, instead of a periodic lapic timer. Message-Id: <20230306070452.292697-1-damien@zamaudio.com>
* lapic timer: Calibrate based on 10 PIT sleeps for 10msDamien Zammit2023-02-261-8/+11
| | | | | | NB: This relies on a fix for QEMU as one-shot PIT mode is currently broken in qemu. Message-Id: <20230226013110.50606-1-damien@zamaudio.com>
* kd_mouse: Fix IBM mouse irq getting stuck and blocking consoleDamien Zammit2023-02-251-2/+5
| | | | | | TESTED: With and without apic/smp Message-Id: <20230225061420.16985-1-damien@zamaudio.com>
* model_dep: Call acpi_apic_init if APIC definedDamien Zammit2023-02-191-2/+3
| | | | | | | | | | | Fixes boot --enable-ncpus=1 with --enable-apic configuration albeit the keyboard is stuck and network cannot be accessed. Error messages: Timeout reached while wating for return value /bin/console: Could not receive return value from daemon process: Connection timed out Message-Id: <20230219022351.25767-1-damien@zamaudio.com>
* Make curr_ipl[] per cpuDamien Zammit2023-02-141-2/+5
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