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* Fix interrupt handlingDamien Zammit2023-10-031-15/+13
| | | | | | | | | | | | | | | | | | | | | | | | | Logic for interrupts: - interrupt.S raises spl (thus IF cleared) - interrupt.S EOI - interrupt.S calls the handler - for pure in-kernel handlers, they do whatever they want with IF cleared. - when a userland handler is registers, queue_intr masks the irq. - interrupt.S lowers spl with splx_cli, thus IF still cleared - iret, that sets IF - later on, userland acks the IRQ, that unmasks the irq The key to this change is that all interrupts, including IPIs, are treated the same way. Eg. the spl level is now raised before an IPI and restored after. Also, EOI is not needed inside irq_acknowledge. With this change and the experimental change not to dispatch threads direct to idle processors in the scheduler, I no longer observe kernel faults, but an occasional hang does occur. Message-Id: <20231002033906.124427-1-damien@zamaudio.com>
* IPI: Do not include support when NCPUS=1Samuel Thibault2023-08-131-0/+4
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* IPI: Rework irq names and fix x86_64 buildSamuel Thibault2023-08-131-3/+8
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* i386/x86_64: Add remote AST via IPI mechanismDamien Zammit2023-08-131-0/+3
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* Acknowledge IRQ *before* calling the handlerSamuel Thibault2023-08-101-23/+24
| | | | | | | | | | | | 5da1aea7ab3c ("Acknoledge interrupt after handler call") moved the IRQ ack to after calling the handler because of overflows. But that was because the interrupts were getting enabled at some point. Now that all spl levels above 0 just disable interrupts, once we have called spl7 we are safe until splx_cli is called (and even that doesn't release interrupts, only the eventual iret will). And if the handler triggers another IRQ, it will be lost, so we do want to ack the IRQ before handling it.
* x86_64: homogeneize with i386 about _call_singleSamuel Thibault2023-08-101-6/+6
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* interrupt.S: No nested interrupts during IPIs && more x86_64 smp supportDamien Zammit2023-08-061-0/+10
| | | | Message-Id: <20230805154843.2003098-1-damien@zamaudio.com>
* fix x86_64 asm for higher kernel addressesLuca Dariz2023-02-121-2/+2
| | | | | | | * x86_64/interrupt.S: use 64-bit registers as variables could be stored at high addresses * x86_64/locore.S: Likewise Message-Id: <20230212172818.1511405-3-luca@orpolo.org>
* intr: Drop irq parameterSamuel Thibault2022-12-241-5/+2
| | | | This is not actually used.
* Update kdb_kintr according to new interrupt stack layoutSamuel Thibault2022-11-271-0/+2
| | | | | | | | e2fcf261076b ("interrupt: Fix saving irq/ipl when linux drivers are disabled") changed the stack layout for interrupt handlers, but missed updating kdb_kintr's code that tries to mangle it. This restores the control-alt-d shortcut.
* interrupt: Fix saving irq/ipl when linux drivers are disabledSamuel Thibault2022-09-171-13/+31
| | | | | | | | | | | | | | When Linux drivers are disabled, in hardclock() the linux_timer_intr() call is dropped, and gcc can tail-recursion-optimize the call to clock_interrupt(). To do so, it overwrites the hardclock() parameters to suit the clock_interrupt parameters layout. This however means it thrashes the backups that the interrupt() function had made of irq/ipl, leading to mayhem. interrupt should thus really properly separate its irq/ipl backups from the interrupt function parameters. Thanks a lot to Etienne Brateau for the tricky investigation!
* fix register corruption in irq on qemuLuca Dariz2022-08-271-6/+6
| | | | | | | | | rbx was used to compute the irq index in iunit and ivect arrays, however it should be preserved by pushing it in to the stack. As a solution, we use rax instead, which is caller-saved. Signed-off-by: Luca Dariz <luca@orpolo.org> Message-Id: <20220205175129.309469-4-luca@orpolo.org>
* ioapic: Refactor EOIDamien Zammit2021-04-051-1/+0
| | | | Message-Id: <20210405115921.184572-2-damien@zamaudio.com>
* Don't call EOI on spurious interruptsDamien Zammit2021-04-051-6/+3
| | | | Message-Id: <20210405052916.174771-4-damien@zamaudio.com>
* Add ioapic support disabled by defaultDamien Zammit2021-04-041-1/+23
| | | | | | | Use --enable-ncpus=x --enable-apic where x > 1 for SMP+APIC support. Use neither for no SMP and old PIC support. Message-Id: <20210404050812.145483-1-damien@zamaudio.com>
* interrupt: Add 64bit variantSamuel Thibault2020-03-281-0/+84
* x86_64/interrupt.S: New file.