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author | Yuqian Yang <crupest@crupest.life> | 2025-02-28 23:13:39 +0800 |
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committer | Yuqian Yang <crupest@crupest.life> | 2025-02-28 23:13:39 +0800 |
commit | dc1f0c4c0096013799416664894c5194dc7e1f52 (patch) | |
tree | 2f5d235f778cd720f4c39ec3e56b77ba6d99f375 /store/works/life/computer-organization-experiment/shift_32.vhdl | |
parent | 7299d424d90b1effb6db69e3476ddd5af72eeba4 (diff) | |
download | crupest-dc1f0c4c0096013799416664894c5194dc7e1f52.tar.gz crupest-dc1f0c4c0096013799416664894c5194dc7e1f52.tar.bz2 crupest-dc1f0c4c0096013799416664894c5194dc7e1f52.zip |
chore(store): move everything to store.
Diffstat (limited to 'store/works/life/computer-organization-experiment/shift_32.vhdl')
-rw-r--r-- | store/works/life/computer-organization-experiment/shift_32.vhdl | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/store/works/life/computer-organization-experiment/shift_32.vhdl b/store/works/life/computer-organization-experiment/shift_32.vhdl new file mode 100644 index 0000000..5cb8425 --- /dev/null +++ b/store/works/life/computer-organization-experiment/shift_32.vhdl @@ -0,0 +1,23 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +use ieee.numeric_std.all; + +entity shift_32 is + port( + D: in std_logic_vector(31 downto 0); + SA: in std_logic_vector(4 downto 0); + Right: in std_logic; + Arith: in std_logic; + SH: out std_logic_vector(31 downto 0) + ); +end entity; + +architecture behavioral of shift_32 is +begin + SH <= + std_logic_vector(signed(D) srl to_integer(unsigned(SA))) when Right = '1' and Arith = '0' + else std_logic_vector(signed(D) sll to_integer(unsigned(SA))) when Right = '0' and Arith = '0' + else std_logic_vector(signed(D) sra to_integer(unsigned(SA))) when Right = '1' and Arith = '1' + else std_logic_vector(signed(D) sla to_integer(unsigned(SA))) when Right = '0' and Arith = '1'; +end behavioral; |