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authorYuqian Yang <crupest@crupest.life>2025-02-12 15:55:21 +0800
committerYuqian Yang <crupest@crupest.life>2025-02-12 15:55:21 +0800
commit1ecfd0ab7f1f511268fd6404dbc110c3c277b48c (patch)
tree49449a4076ded9bd937a51679318edbe2a532cae /works/life/computer-organization-experiment/multiplexer_8_2.vhdl
parent55d8b025e8d6ea971e8ee5762c892405fedc316b (diff)
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+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity multiplexer_8_2 is
+ port (A0, A1 : in std_logic_vector(7 downto 0); S : in std_logic; Y : out std_logic_vector(7 downto 0));
+end multiplexer_8_2;
+
+architecture behaviour of multiplexer_8_2 is
+begin
+ Y <= A0 when S = '0' else A1;
+end behaviour;