import(life): ...

8 files changed, 121 insertions, 0 deletions

diff --git a/works/life/.DS_Store b/works/life/.DS_Store
index c4a5fe2..a51aa91 100644
--- a/works/life/.DS_Store
+++ b/works/life/.DS_Store
diff --git a/works/life/computer-organization-experiment/.DS_Store b/works/life/computer-organization-experiment/.DS_Store
new file mode 100644
index 0000000..218d033
--- /dev/null
+++ b/works/life/computer-organization-experiment/.DS_Store
diff --git a/works/life/computer-organization-experiment/.gitignore b/works/life/computer-organization-experiment/.gitignore
new file mode 100644
index 0000000..c795b05
--- /dev/null
+++ b/works/life/computer-organization-experiment/.gitignore
@@ -0,0 +1 @@
+build
\ No newline at end of file
diff --git a/works/life/computer-organization-experiment/Makefile b/works/life/computer-organization-experiment/Makefile
new file mode 100644
index 0000000..d44613c
--- /dev/null
+++ b/works/life/computer-organization-experiment/Makefile
@@ -0,0 +1,21 @@
+all: build/counter_4.o build/test_bench.o build/full_adder_1.o build/test_bench
+
+build:
+	mkdir -p build
+
+build/counter_4.o: build counter_4.vhdl
+	ghdl analyze --workdir=build -fsynopsys counter_4.vhdl
+
+build/full_adder_1.o: build full_adder_1.vhdl
+	ghdl analyze --workdir=build -fsynopsys full_adder_1.vhdl
+
+build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o
+	ghdl analyze --workdir=build -fsynopsys test_bench.vhdl
+
+build/test_bench: build/counter_4.o build/full_adder_1.o build/test_bench.o
+	ghdl elaborate --workdir=build -fsynopsys -o build/test_bench test_bench 
+
+.PHONY: all clean
+
+clean:
+	rm -r build
diff --git a/works/life/computer-organization-experiment/counter_4.vhdl b/works/life/computer-organization-experiment/counter_4.vhdl
new file mode 100644
index 0000000..23c1807
--- /dev/null
+++ b/works/life/computer-organization-experiment/counter_4.vhdl
@@ -0,0 +1,19 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+ENTITY counter_4 IS
+  PORT (CLK:IN STD_LOGIC;
+    CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
+END counter_4;
+ARCHITECTURE behavior OF counter_4 IS
+BEGIN
+  PROCESS(CLK)
+    VARIABLE CQI:STD_LOGIC_VECTOR(3 DOWNTO 0) := B"0000";
+  BEGIN
+    IF CLK'EVENT AND CLK='1' THEN
+      CQI := CQI + 1;
+    END IF;
+    CQ<=CQI;
+  END PROCESS;
+END behavior;
diff --git a/works/life/computer-organization-experiment/full_adder_1.vhdl b/works/life/computer-organization-experiment/full_adder_1.vhdl
new file mode 100644
index 0000000..9b269bf
--- /dev/null
+++ b/works/life/computer-organization-experiment/full_adder_1.vhdl
@@ -0,0 +1,13 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity full_adder_1 is
+    port (A, B, CI:in std_logic; S, CO: out std_logic);
+end full_adder_1;
+
+architecture behavior of full_adder_1 is
+begin
+    S <= (A XOR B) XOR CI;
+    CO <= (A AND B) OR (B AND CI) OR (CI AND A);
+end architecture;
diff --git a/works/life/computer-organization-experiment/hdl-prj.json b/works/life/computer-organization-experiment/hdl-prj.json
new file mode 100644
index 0000000..91428c1
--- /dev/null
+++ b/works/life/computer-organization-experiment/hdl-prj.json
@@ -0,0 +1,22 @@
+{
+    "options": {
+        "ghdl_analysis": [
+            "-fsynopsys",
+            "--workdir=build"
+        ]
+    },
+    "files": [
+        {
+            "file": "counter_4.vhdl",
+            "language": "vhdl"
+        },
+        {
+            "file": "full_adder_1.vhdl",
+            "language": "vhdl"
+        },
+        {
+            "file": "test_bench.vhdl",
+            "language": "vhdl"
+        }
+    ]
+}
\ No newline at end of file
diff --git a/works/life/computer-organization-experiment/test_bench.vhdl b/works/life/computer-organization-experiment/test_bench.vhdl
new file mode 100644
index 0000000..be15df9
--- /dev/null
+++ b/works/life/computer-organization-experiment/test_bench.vhdl
@@ -0,0 +1,45 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity test_bench is
+end test_bench;
+
+architecture test_counter_4 of test_bench is
+  signal CLK : STD_LOGIC;
+  signal CQ: STD_LOGIC_VECTOR(3 DOWNTO 0);
+begin
+    counter: entity work.counter_4(behavior)
+        port map (CLK, CQ);
+    stimulus: process is
+    begin
+      for count_value in 0 to 2 ** 4 - 1 loop
+        if count_value mod 2 = 0 then
+          CLK <= '1';
+          wait for 5 ns;
+        else
+          CLK <= '0';
+          wait for 5 ns;
+        end if;
+      end loop;
+    end process stimulus;
+end architecture test_counter_4;
+
+
+architecture test_full_adder_1 of test_bench is
+  subtype v3 is std_logic_vector(2 downto 0);
+  signal I: v3 := B"000";
+  signal S, CO : STD_LOGIC;
+begin
+    adder: entity work.full_adder_1(behavior)
+        port map (I(2), I(1), I(0), S, CO);
+    stimulus: process is
+      variable ii : v3 := B"000";
+    begin
+      loop
+        ii := ii + 1;
+        I <= ii;
+        wait for 5 ns;
+      end loop;
+    end process stimulus;
+end architecture test_full_adder_1;