import(life): ...

3 files changed, 249 insertions, 1096 deletions

diff --git a/works/life/computer-organization-experiment/cpu.vhdl b/works/life/computer-organization-experiment/cpu.vhdl
index f1a7d65..aca35cf 100644
--- a/works/life/computer-organization-experiment/cpu.vhdl
+++ b/works/life/computer-organization-experiment/cpu.vhdl
@@ -4,6 +4,7 @@ use ieee.std_logic_1164.all;
 package cru is
     subtype word is std_logic_vector(31 downto 0);
     constant clock_time : time := 10 ns;
+    constant ram_clock_time: time := 2.5 ns;
 end package;
 
 library ieee;
@@ -35,13 +36,36 @@ end architecture;
 
 library ieee;
 use ieee.std_logic_1164.all;
+use work.cru.all;
+
+entity reg_file_clock is
+    port(CLK: out std_logic);
+end entity;
+
+architecture Behavioral of reg_file_clock is
+    signal V: std_logic := '1';
+begin
+    l: process is
+    begin
+        CLK <= V;
+        wait for 1 ns;
+        loop
+            V <= not V;
+            wait for 1 ps;
+            CLK <= V;
+            wait for clock_time;
+        end loop;
+    end process;
+end architecture;
+
+library ieee;
+use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use ieee.std_logic_unsigned.all;
 use work.cru.all;
 
 entity register_file is
     port (
-        CLK: in std_logic;
         ENABLE: in std_logic;
         R1, R2, W: in std_logic_vector(4 downto 0);
         WD: in std_logic_vector(31 downto 0);
@@ -52,7 +76,10 @@ end entity;
 architecture Behavioral of register_file is
     type reg_file_type is array (0 to 31) of std_logic_vector(31 downto 0);
     signal reg_file: reg_file_type := (others => (others => '0'));
+    signal CLK : std_logic;
 begin
+    clock: entity work.reg_file_clock
+        port map (CLK);
     process (CLK)
     begin
         if rising_edge(CLK) then
@@ -91,13 +118,11 @@ begin
          else std_logic_vector(signed(A) sll to_integer(unsigned(B))) when ALUC ?= B"0011"
          else std_logic_vector(signed(A) srl to_integer(unsigned(B))) when ALUC ?= B"0111"
          else std_logic_vector(signed(A) sra to_integer(unsigned(B))) when ALUC ?= B"1111";
-    Z <= S ?= X"00000000";
+    Z <= S ?= X"00000000" after 10 ps;
 end architecture;
 
 library ieee;
 use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
 use work.cru.all;
 
 entity clock is
@@ -113,16 +138,41 @@ end architecture;
 
 library ieee;
 use ieee.std_logic_1164.all;
+use work.cru.all;
+
+entity ram_clock is
+    port(CLK: out std_logic);
+end entity;
+
+architecture Behavioral of ram_clock is
+    signal V: std_logic := '0';
+begin
+    l: process is
+    begin
+        CLK <= V;
+        wait for 500 ps;
+        loop
+            V <= not V;
+            wait for 1 ps;
+            CLK <= V;
+            wait for ram_clock_time;
+        end loop;
+    end process;
+end architecture;
+
+library ieee;
+use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
 use work.cru.all;
 
 entity ram is
-    port(CLK: in std_logic;
-        R: out word;
-        W: in word;
-        ADDR: in word;
-        ENABLE: in std_logic
+    port(
+        R_DATA: out word;
+        W_DATA: in word;
+        R_ADDR: in word;
+        W_ADDR: in word;
+        READ: in std_logic;
+        WRITE: in std_logic
     );
 end entity;
 
@@ -130,7 +180,7 @@ architecture Behavioral of ram is
     type memory_type is array (0 to 16#30#) of word;
     signal memory: memory_type := (
                 X"3c010000",
-                X"34240020",
+                X"34240080",
                 X"20050004",
                 X"0c000018",
                 X"ac820000",
@@ -168,14 +218,17 @@ architecture Behavioral of ram is
                 others => (others => '0')
         );
     signal V: std_logic := '0';
+    signal CLK: std_logic;
 begin
+    clock: entity work.ram_clock
+        port map (CLK);
     b: process(CLK) is 
     begin
-        if rising_edge(CLK) then
-            R <= memory(to_integer(unsigned(ADDR)) / 4);
+        if rising_edge(CLK) and READ = '1' then
+            R_DATA <= memory(to_integer(unsigned(R_ADDR)) / 4);
         end if;
-        if falling_edge(CLK) and ENABLE = '1' then
-            memory(to_integer(unsigned(ADDR)) / 4) <= W;
+        if falling_edge(CLK) and WRITE = '1' then
+            memory(to_integer(unsigned(W_ADDR)) / 4) <= W_DATA;
         end if;
     end process;
 end architecture;
@@ -198,17 +251,18 @@ architecture Behavioral of cpu is
 
     signal ins: word;
 
-    signal enable_mem: std_logic;
-    signal write_mem: std_logic := '0';
-    signal addr: word := X"00000000";
-    signal mem_w: word;
-    signal mem_r: word;
+    signal mem_r_addr: word := X"00000000";
+    signal mem_w_addr: word := X"00000000";
+    signal mem_r_data: word;
+    signal mem_w_data: word := X"00000000";
+    signal mem_read: std_logic := '0';
+    signal mem_write: std_logic := '0';
 
     signal WRITE_REG: std_logic := '0';
     signal R1: std_logic_vector(4 downto 0) := B"00000";
     signal R2: std_logic_vector(4 downto 0)  := B"00000";
     signal W: std_logic_vector(4 downto 0)  := B"00000";
-    signal WD: std_logic_vector(31 downto 0);
+    signal WD: std_logic_vector(31 downto 0) := X"00000000";
     signal RD1: std_logic_vector(31 downto 0) := X"00000000";
     signal RD2: std_logic_vector(31 downto 0) := X"00000000";
 
@@ -227,7 +281,6 @@ begin
         );
     reg: entity work.register_file
         port map(
-            CLK => CLK,
             ENABLE => WRITE_REG,
             R1 => R1,
             R2 => R2,
@@ -247,84 +300,112 @@ begin
 
     ram: entity work.ram
         port map (
-            CLK => CLK,
-            R => mem_r,
-            W => mem_w,
-            ADDR => addr,
-            ENABLE => write_mem
+            R_DATA => mem_r_data,
+            W_DATA => mem_w_data,
+            R_ADDR => mem_r_addr,
+            W_ADDR => mem_w_addr,
+            READ => mem_read,
+            WRITE => mem_write
         );
 
     logic: process is
     begin
         wait until rising_edge(CLK);
-        wait for 100 ps;
 
-        addr <= pc;
+        wait for 250 ps;
+
+        mem_read <= '1';
+        mem_r_addr <= pc;
         pc_to_write <= pc + 4;
 
-        wait for 1 ns;
-        ins <= mem_r;
+        wait for 500 ps;
+
+        ins <= mem_r_data;
+
+        mem_write <= '0';
 
         WRITE_REG <= '0';
+        
+        wait for 100 ps;
 
-        if ins(31 downto 27) = B"00001" then -- j / jal
+        if ins(31 downto 27) = B"00001" then -- j / jal, not read reg
             if ins(26) = '1' then -- jal
                 W <= B"11111";
-                WD <= pc;
+                WD <= pc + 4;
                 WRITE_REG <= '1';
             end if;
-            pc_to_write <= (25 downto 0 => ins(25 downto 0), others => '0');
+
+            ALUC <= B"0011";
+            A <= (25 downto 0 => ins(25 downto 0), others => '0');
+            B <= X"00000002";
+            wait for 100 ps;
+            pc_to_write <= S; 
         elsif ins(31 downto 26) = B"000000" then
             if ins(5) = '1' then
                 R1 <= ins(25 downto 21);
                 R2 <= ins(20 downto 16);
-                ALUC <= ins(3 downto 0);
 
-                wait for 100 ps;
+                wait for 500 ps;
 
+                ALUC <= ins(3 downto 0);
                 A <= RD1;
                 B <= RD2;
+
+                wait for 100 ps;
+
                 W <= ins(15 downto 11);
                 WRITE_REG <= '1';
                 WD <= S;
             elsif ins(3) = '0' then
                 R1 <= ins(20 downto 16);
+
+                wait for 500 ps;
+
                 ALUC(3 downto 2) <= ins(1 downto 0);
                 ALUC(1 downto 0) <= B"11";
+                A <= RD1;
+                B <= (4 downto 0 => ins(10 downto 6), others => '0');
 
                 wait for 100 ps;
 
-                A <= RD1;
-                B <= (4 downto 0 => ins(10 downto 6), others => '0');
                 W <= ins(15 downto 11);
                 WRITE_REG <= '1';
                 WD <= S;
             else
                 R1 <= ins(25 downto 21);
-                WRITE_REG <= '0';
 
-                wait for 100 ps;
+                wait for 500 ps;
 
                 pc_to_write <= RD1;
             end if;
         else
             if ins(31) = '1' then
-                enable_mem <= '1';
                 R1 <= ins(25 downto 21);
-                ALUC <= B"0000";
+                R2 <= ins(20 downto 16);
 
-                wait for 100 ps;
+                wait for 500 ps;
 
+                ALUC <= B"0000";
                 A <= RD1;
                 B <= (15 downto 0 => ins(15 downto 0), others => '0' );
+
+                wait for 100 ps;
+
                 if ins(29) = '1' then
-                    W <= ins(20 downto 16);
-                    write_mem <= '0';
-                else
                     R2 <= ins(20 downto 16);
-                    write_mem <= '1';
+                    mem_write <= '1';
+                    mem_w_addr <= S;
+                    mem_w_data <= RD2;
+
+                else
+                    W <= ins(20 downto 16);
+                    mem_read <= '1';
+                    mem_r_addr <= S;
+
+                    wait for ram_clock_time * 2;
 
-                    wait for 100 ps;
+                    WD <= mem_r_data;
+                    WRITE_REG <= '1';
                 end if;
             elsif ins(29 downto 26) = B"1111" then
                 WRITE_REG <= '1';
@@ -332,43 +413,42 @@ begin
                 WD(31 downto 16) <= ins(15 downto 0);
             elsif ins(29) = '1' then
                 R1 <= ins(25 downto 21);
-                ALUC <= ins(29 downto 26);
 
-                wait for 100 ps;
+                wait for 500 ps;
 
+                ALUC <= ins(29 downto 26);
                 A <= RD1;
                 B(15 downto 0) <= ins(15 downto 0);
-                B(31 downto 16) <= X"0000";
+                if ins(15) = '0' then
+                    B(31 downto 16) <= X"0000";
+                else
+                    B(31 downto 16) <= X"FFFF";
+                end if;
+
+                wait for 100 ps;
+
                 W <= ins(20 downto 16);
                 WRITE_REG <= '1';
                 WD <= S;
             else
                 R1 <= ins(25 downto 21);
                 R2 <= ins(20 downto 16);
-                ALUC <= B"0010";
                 
-                wait for 100 ps;
+                wait for 500 ps;
                 
+                ALUC <= B"0010";
                 A <= RD1;
                 B <= RD2;
-                if Z = '1' then
-                    pc_to_write <= pc_to_write + to_integer(unsigned(ins(15 downto 0)) * 4);
+
+                wait for 100 ps;
+
+                if Z = '1' xor ins(26) = '1' then
+                    pc_to_write <= pc_to_write + to_integer(signed(ins(15 downto 0)) * 4);
                 end if;
                 WRITE_REG <= '0';
             end if;
         end if;
 
-        if enable_mem then
-            if write_mem then
-                WRITE_REG <= '0';
-                mem_w <= RD2;
-            else
-                WRITE_REG <= '1';
-                WD <= mem_r;
-            end if;
-        else
-            write_mem <= '0';
-        end if;
     end process;
 end architecture;
 
diff --git a/works/life/computer-organization-experiment/out.ghw b/works/life/computer-organization-experiment/out.ghw
index 10d4b17..81d1df7 100644
--- a/works/life/computer-organization-experiment/out.ghw
+++ b/works/life/computer-organization-experiment/out.ghw
diff --git a/works/life/computer-organization-experiment/out.vcd b/works/life/computer-organization-experiment/out.vcd
index 5bc0ca7..a47fb22 100644
--- a/works/life/computer-organization-experiment/out.vcd
+++ b/works/life/computer-organization-experiment/out.vcd
@@ -1,5 +1,5 @@
 $date
-  Sat Dec 25 16:11:16 2021
+  Sun Dec 26 07:20:30 2021
 $end
 $version
   GHDL v0
@@ -32,56 +32,63 @@ $var reg 1 $ clk $end
 $var reg 32 % pc[31:0] $end
 $var reg 32 & pc_to_write[31:0] $end
 $var reg 32 ' ins[31:0] $end
-$var reg 1 ( enable_mem $end
-$var reg 1 ) write_mem $end
-$var reg 32 * addr[31:0] $end
-$var reg 32 + mem_w[31:0] $end
-$var reg 32 , mem_r[31:0] $end
-$var reg 1 - write_reg $end
-$var reg 5 . r1[4:0] $end
-$var reg 5 / r2[4:0] $end
-$var reg 5 0 w[4:0] $end
-$var reg 32 1 wd[31:0] $end
-$var reg 32 2 rd1[31:0] $end
-$var reg 32 3 rd2[31:0] $end
-$var reg 32 4 a[31:0] $end
-$var reg 32 5 b[31:0] $end
-$var reg 4 6 aluc[3:0] $end
-$var reg 32 7 s[31:0] $end
-$var reg 1 8 z $end
+$var reg 32 ( mem_r_addr[31:0] $end
+$var reg 32 ) mem_w_addr[31:0] $end
+$var reg 32 * mem_r_data[31:0] $end
+$var reg 32 + mem_w_data[31:0] $end
+$var reg 1 , mem_read $end
+$var reg 1 - mem_write $end
+$var reg 1 . write_reg $end
+$var reg 5 / r1[4:0] $end
+$var reg 5 0 r2[4:0] $end
+$var reg 5 1 w[4:0] $end
+$var reg 32 2 wd[31:0] $end
+$var reg 32 3 rd1[31:0] $end
+$var reg 32 4 rd2[31:0] $end
+$var reg 32 5 a[31:0] $end
+$var reg 32 6 b[31:0] $end
+$var reg 4 7 aluc[3:0] $end
+$var reg 32 8 s[31:0] $end
+$var reg 1 9 z $end
 $scope module pc_reg $end
-$var reg 1 9 clk $end
-$var reg 1 : enable $end
-$var reg 32 ; w[31:0] $end
-$var reg 32 < r[31:0] $end
-$var reg 32 = v[31:0] $end
+$var reg 1 : clk $end
+$var reg 1 ; enable $end
+$var reg 32 < w[31:0] $end
+$var reg 32 = r[31:0] $end
+$var reg 32 > v[31:0] $end
 $upscope $end
 $scope module reg $end
-$var reg 1 > clk $end
-$var reg 1 ? enable $end
-$var reg 5 @ r1[4:0] $end
-$var reg 5 A r2[4:0] $end
-$var reg 5 B w[4:0] $end
-$var reg 32 C wd[31:0] $end
-$var reg 32 D rd1[31:0] $end
-$var reg 32 E rd2[31:0] $end
+$var reg 1 ? clk $end
+$var reg 1 @ enable $end
+$var reg 5 A r1[4:0] $end
+$var reg 5 B r2[4:0] $end
+$var reg 5 C w[4:0] $end
+$var reg 32 D wd[31:0] $end
+$var reg 32 E rd1[31:0] $end
+$var reg 32 F rd2[31:0] $end
 $comment reg_file is not handled $end
 $upscope $end
 $scope module alu $end
-$var reg 32 F a[31:0] $end
-$var reg 32 G b[31:0] $end
-$var reg 4 H aluc[3:0] $end
-$var reg 32 I s[31:0] $end
-$var reg 1 J z $end
+$var reg 32 G a[31:0] $end
+$var reg 32 H b[31:0] $end
+$var reg 4 I aluc[3:0] $end
+$var reg 32 J s[31:0] $end
+$var reg 1 K z $end
 $upscope $end
 $scope module ram $end
-$var reg 1 K clk $end
-$var reg 32 L r[31:0] $end
-$var reg 32 M w[31:0] $end
-$var reg 32 N addr[31:0] $end
-$var reg 1 O enable $end
+$var reg 32 L r_data[31:0] $end
+$var reg 32 M w_data[31:0] $end
+$var reg 32 N r_addr[31:0] $end
+$var reg 32 O w_addr[31:0] $end
+$var reg 1 P read $end
+$var reg 1 Q write $end
 $comment memory is not handled $end
-$var reg 1 P v $end
+$var reg 1 R v $end
+$var reg 1 S clk $end
+$scope module clock $end
+$var reg 1 T clk $end
+$var reg 1 U v $end
+$upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -94,1018 +101,84 @@ $enddefinitions $end
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 bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU &
 bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU '
-U(
-0)
-b00000000000000000000000000000000 *
-bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU +
-bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU ,
+b00000000000000000000000000000000 (
+b00000000000000000000000000000000 )
+bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU *
+b00000000000000000000000000000000 +
+0,
 0-
-b00000 .
+0.
 b00000 /
 b00000 0
-bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU 1
+b00000 1
 bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU 2
 bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU 3
-b00000000000000000000000000000000 4
+bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU 4
 b00000000000000000000000000000000 5
-b0000 6
-b00000000000000000000000000000000 7
-18
-09
-1:
-bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU ;
+b00000000000000000000000000000000 6
+b0000 7
+b00000000000000000000000000000000 8
+19
+0:
+1;
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-b00000000000000000000000000000000 =
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+bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU =
+b00000000000000000000000000000000 >
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-b00000 @
+0@
 b00000 A
 b00000 B
-bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU C
+b00000 C
 bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU D
 bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU E
-b00000000000000000000000000000000 F
+bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU F
 b00000000000000000000000000000000 G
-b0000 H
-b00000000000000000000000000000000 I
-1J
-0K
+b00000000000000000000000000000000 H
+b0000 I
+b00000000000000000000000000000000 J
+1K
 bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU L
-bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU M
+b00000000000000000000000000000000 M
 b00000000000000000000000000000000 N
-0O
+b00000000000000000000000000000000 O
 0P
+0Q
+0R
+0S
+0T
+0U
+#200000
+#2700000
+1U
+#5200000
+1S
+1T
+0U
+#7700000
+0S
+0T
+1U
 #10000000
 1!
 1"
 1#
 1$
 b00000000000000000000000000000000 %
-b00111100000000010000000000000000 ,
-b00000000000000000000000000000000 2
 b00000000000000000000000000000000 3
-19
-b00000000000000000000000000000000 <
-1>
-b00000000000000000000000000000000 D
+b00000000000000000000000000000000 4
+1:
+b00000000000000000000000000000000 =
+1?
 b00000000000000000000000000000000 E
-1K
-b00111100000000010000000000000000 L
+b00000000000000000000000000000000 F
 #10100000
-b00000000000000000000000000000001 &
-b00000000000000000000000000000001 ;
-#11100000
-b00111100000000010000000000000000 '
-bUUUUU .
-bUUUUU /
-b0010 6
-bUUUUU @
-bUUUUU A
-b0010 H
-#11200000
-#20000000
-0!
-0"
-0#
-0$
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-b00000000000000000000000000000001 =
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-0K
-#30000000
-1!
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-1#
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-b00000000000000000000000000000001 %
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-#30100000
-b00000000000000000000000000000010 &
-b00000000000000000000000000000001 *
-b00000000000000000000000000000010 ;
-b00000000000000000000000000000001 N
-#31100000
-1-
-b00001 0
-b0000000000000000UUUUUUUUUUUUUUUU 1
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-b0000000000000000UUUUUUUUUUUUUUUU C
-#40000000
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-0#
-0$
-09
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-#50000000
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-b00000000000000000000000000000010 %
-b00110100001001000000000000100000 ,
-19
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-1>
-1K
-b00110100001001000000000000100000 L
-#50100000
-b00000000000000000000000000000011 &
-b00000000000000000000000000000010 *
-b00000000000000000000000000000011 ;
-b00000000000000000000000000000010 N
-#51100000
-b00110100001001000000000000100000 '
-#60000000
-0!
-0"
-0#
-0$
-09
-b00000000000000000000000000000011 =
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-b00000000000000000000000000000011 %
-b00100000000001010000000000000100 ,
-19
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-b00000000000000000000000000000100 ;
-b00000000000000000000000000000011 N
-#71100000
-b00100000000001010000000000000100 '
-0-
-b00001 .
-b1101 6
-0?
-b00001 @
-b1101 H
-#71200000
-1-
-b00101 0
-b00000000000000000000000000000000 1
-b00000000000000000000000000000100 5
-b00000000000000000000000000000100 7
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-b00101 B
-b00000000000000000000000000000000 C
-b00000000000000000000000000000100 G
-b00000000000000000000000000000100 I
-0J
-#80000000
-0!
-0"
-0#
-0$
-09
-b00000000000000000000000000000100 =
-0>
-0K
-#90000000
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-1#
-1$
-b00000000000000000000000000000100 %
-b00001100000000000000000000011000 ,
-b0000000000000000UUUUUUUUUUUUUUUU 2
-19
+1,
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-1>
-b0000000000000000UUUUUUUUUUUUUUUU D
-1K
-b00001100000000000000000000011000 L
-#90100000
-b00000000000000000000000000000101 &
-b00000000000000000000000000000100 *
-b00000000000000000000000000000101 ;
-b00000000000000000000000000000100 N
-#91100000
-b00001100000000000000000000011000 '
-0-
-b00000 .
-b1000 6
-0?
-b00000 @
-b1000 H
-#91200000
-1-
-b00000 0
-b00000000000000000000000000000100 1
-b0000000000000000UUUUUUUUUUUUUUUU 4
-b00000000000000000000000000011000 5
-bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX 7
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-b00000 B
-b00000000000000000000000000000100 C
-b0000000000000000UUUUUUUUUUUUUUUU F
-b00000000000000000000000000011000 G
-bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX I
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-#100000000
-0!
-0"
-0#
-0$
-09
-b00000000000000000000000000000101 =
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-#110000000
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-b00000000000000000000000000000101 %
-b10101100100000100000000000000000 ,
-b00000000000000000000000000000100 2
-b00000000000000000000000000000100 3
-19
-b00000000000000000000000000000101 <
-1>
-b00000000000000000000000000000100 D
-b00000000000000000000000000000100 E
-1K
-b10101100100000100000000000000000 L
-#110100000
-b00000000000000000000000000000110 &
-b00000000000000000000000000000101 *
-b00000000000000000000000000000110 ;
-b00000000000000000000000000000101 N
-#111100000
-b00000000000000000000000000011000 &
-b10101100100000100000000000000000 '
-b11111 0
-b00000000000000000000000000000101 1
-b00000000000000000000000000011000 ;
-b11111 B
-b00000000000000000000000000000101 C
-#120000000
-0!
-0"
-0#
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-b00000000000000000000000000011000 =
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-b10001100100010010000000000000000 ,
-19
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-b10001100100010010000000000000000 L
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-b00000000000000000000000000011000 *
-b00000000000000000000000000011001 ;
-b00000000000000000000000000011000 N
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-b00000 0
-b00000000000000000000000000000000 1
-b00000000000000000000000000000000 5
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-b00000000000000000000000000000100 M
-#180000000
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-19
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-b00000000000000000000000000011100 N
-#211100000
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