import(life): Add computer organization 5.

6 files changed, 80 insertions, 38 deletions

diff --git a/works/life/computer-organization-experiment/Makefile b/works/life/computer-organization-experiment/Makefile
index 96a830d..8777267 100644
--- a/works/life/computer-organization-experiment/Makefile
+++ b/works/life/computer-organization-experiment/Makefile
@@ -4,34 +4,37 @@ build:
 	mkdir -p build
 
 build/adder_1.o: build adder_1.vhdl
-	ghdl analyze --workdir=build -fsynopsys adder_1.vhdl
+	ghdl analyze --std=08 --workdir=build -fsynopsys adder_1.vhdl
 
 build/adder_8.o: build adder_8.vhdl
-	ghdl analyze --workdir=build -fsynopsys adder_8.vhdl
+	ghdl analyze --std=08 --workdir=build -fsynopsys adder_8.vhdl
 
 build/adder_32.o: build adder_32.vhdl
-	ghdl analyze --workdir=build -fsynopsys adder_32.vhdl
+	ghdl analyze --std=08 --workdir=build -fsynopsys adder_32.vhdl
 
 build/counter_4.o: build counter_4.vhdl
-	ghdl analyze --workdir=build -fsynopsys counter_4.vhdl
+	ghdl analyze --std=08 --workdir=build -fsynopsys counter_4.vhdl
 
 build/full_adder_1.o: build full_adder_1.vhdl
-	ghdl analyze --workdir=build -fsynopsys full_adder_1.vhdl
+	ghdl analyze --std=08 --workdir=build -fsynopsys full_adder_1.vhdl
 
 build/multiplexer_1_2.o: build multiplexer_1_2.vhdl
-	ghdl analyze --workdir=build -fsynopsys multiplexer_1_2.vhdl
+	ghdl analyze --std=08 --workdir=build -fsynopsys multiplexer_1_2.vhdl
 
 build/multiplexer_8_2.o: build multiplexer_8_2.vhdl
-	ghdl analyze --workdir=build -fsynopsys multiplexer_8_2.vhdl
+	ghdl analyze --std=08 --workdir=build -fsynopsys multiplexer_8_2.vhdl
 
 build/multiplexer_32_2.o: build multiplexer_32_2.vhdl
-	ghdl analyze --workdir=build -fsynopsys multiplexer_32_2.vhdl
+	ghdl analyze --std=08 --workdir=build -fsynopsys multiplexer_32_2.vhdl
 
-build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o build/multiplexer_1_2.o build/multiplexer_8_2.o build/multiplexer_32_2.o build/adder_1.o build/adder_8.o build/adder_32.o
-	ghdl analyze --workdir=build -fsynopsys test_bench.vhdl
+build/shift_32.o: build shift_32.vhdl
+	ghdl analyze --std=08 --workdir=build -fsynopsys shift_32.vhdl
+
+build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o build/multiplexer_1_2.o build/multiplexer_8_2.o build/multiplexer_32_2.o build/adder_1.o build/adder_8.o build/adder_32.o build/shift_32.o
+	ghdl analyze --std=08 --workdir=build -fsynopsys test_bench.vhdl
 
 build/test_bench: build/test_bench.o
-	ghdl elaborate --workdir=build -fsynopsys -o build/test_bench test_bench 
+	ghdl elaborate --std=08 --workdir=build -fsynopsys -o build/test_bench test_bench 
 
 .PHONY: all clean
 
diff --git a/works/life/computer-organization-experiment/multiplexer_1_2.vhdl b/works/life/computer-organization-experiment/multiplexer_1_2.vhdl
index 3949e63..1fdeb0f 100644
--- a/works/life/computer-organization-experiment/multiplexer_1_2.vhdl
+++ b/works/life/computer-organization-experiment/multiplexer_1_2.vhdl
@@ -8,13 +8,5 @@ end multiplexer_1_2;
 
 architecture behaviour of multiplexer_1_2 is
 begin
-  b: process is
-  begin
-    if S = '1' then
-      Y <= A1;
-    else
-      Y <= A0;
-    end if;
-    wait for 1 ps;
-  end process b;
+  Y <= A0 when S = '0' else A1;
 end behaviour;
diff --git a/works/life/computer-organization-experiment/multiplexer_32_2.vhdl b/works/life/computer-organization-experiment/multiplexer_32_2.vhdl
index 563874d..1c7d626 100644
--- a/works/life/computer-organization-experiment/multiplexer_32_2.vhdl
+++ b/works/life/computer-organization-experiment/multiplexer_32_2.vhdl
@@ -8,13 +8,5 @@ end multiplexer_32_2;
 
 architecture behaviour of multiplexer_32_2 is
 begin
-  b: process is
-  begin
-    if S = '1' then
-      Y <= A1;
-    else
-      Y <= A0;
-    end if;
-    wait for 1 ps;
-  end process b;
+  Y <= A0 when S = '0' else A1;
 end behaviour;
diff --git a/works/life/computer-organization-experiment/multiplexer_8_2.vhdl b/works/life/computer-organization-experiment/multiplexer_8_2.vhdl
index d9e80f8..6be0bd2 100644
--- a/works/life/computer-organization-experiment/multiplexer_8_2.vhdl
+++ b/works/life/computer-organization-experiment/multiplexer_8_2.vhdl
@@ -8,13 +8,5 @@ end multiplexer_8_2;
 
 architecture behaviour of multiplexer_8_2 is
 begin
-  b: process is
-  begin
-    if S = '1' then
-      Y <= A1;
-    else
-      Y <= A0;
-    end if;
-    wait for 1 ps;
-  end process b;
+  Y <= A0 when S = '0' else A1;
 end behaviour;
diff --git a/works/life/computer-organization-experiment/shift_32.vhdl b/works/life/computer-organization-experiment/shift_32.vhdl
new file mode 100644
index 0000000..5cb8425
--- /dev/null
+++ b/works/life/computer-organization-experiment/shift_32.vhdl
@@ -0,0 +1,23 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+entity shift_32 is
+  port(
+    D: in std_logic_vector(31 downto 0);
+    SA: in std_logic_vector(4 downto 0);
+    Right: in std_logic;
+    Arith: in std_logic;
+    SH: out std_logic_vector(31 downto 0)
+  );
+end entity;
+
+architecture behavioral of shift_32 is
+begin
+  SH <= 
+         std_logic_vector(signed(D) srl to_integer(unsigned(SA))) when Right = '1' and Arith = '0'
+    else std_logic_vector(signed(D) sll to_integer(unsigned(SA))) when Right = '0' and Arith = '0'
+    else std_logic_vector(signed(D) sra to_integer(unsigned(SA)))  when Right = '1' and Arith = '1'
+    else std_logic_vector(signed(D) sla to_integer(unsigned(SA))) when Right = '0' and Arith = '1';
+end behavioral;
diff --git a/works/life/computer-organization-experiment/test_bench.vhdl b/works/life/computer-organization-experiment/test_bench.vhdl
index 64daf7f..6e5e9e8 100644
--- a/works/life/computer-organization-experiment/test_bench.vhdl
+++ b/works/life/computer-organization-experiment/test_bench.vhdl
@@ -84,3 +84,43 @@ begin
     end loop;
   end process stimulus;
 end architecture test_adder_32;
+
+architecture test_shift_32 of test_bench is
+  signal D: std_logic_vector(31 downto 0) := B"00000000000000000000000000000011";
+  signal SA: std_logic_vector(4 downto 0) := B"00000";
+  signal Right: std_logic;
+  signal Arith: std_logic;
+  signal SH: std_logic_vector(31 downto 0);
+begin
+  shift: entity work.shift_32(behavioral)
+      port map (D, SA, Right, Arith, SH);
+  stimulus: process is
+  begin
+    loop
+      D <= B"00000000000000000000000000000011" and D;
+      Right <= '0';
+      Arith <= '0';
+      wait for 5 ns;
+      Arith <= '1';
+      wait for 5 ns;
+      Right <= '1';
+      Arith <= '0';
+      wait for 5 ns;
+      Arith <= '1';
+      wait for 5 ns;
+      D <= B"10000000000000000000000000000000" or D;
+      Right <= '0';
+      Arith <= '0';
+      wait for 5 ns;
+      Arith <= '1';
+      wait for 5 ns;
+      Right <= '1';
+      Arith <= '0';
+      wait for 5 ns;
+      Arith <= '1';
+      wait for 5 ns;
+
+      SA <= SA + 1;
+    end loop;
+  end process stimulus;
+end architecture test_shift_32;