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-rw-r--r--works/life/computer-organization-experiment/counter_4.vhdl19
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diff --git a/works/life/computer-organization-experiment/counter_4.vhdl b/works/life/computer-organization-experiment/counter_4.vhdl
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--- a/works/life/computer-organization-experiment/counter_4.vhdl
+++ /dev/null
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-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-ENTITY counter_4 IS
- PORT (CLK:IN STD_LOGIC;
- CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
-END counter_4;
-ARCHITECTURE behavior OF counter_4 IS
-BEGIN
- PROCESS(CLK)
- VARIABLE CQI:STD_LOGIC_VECTOR(3 DOWNTO 0) := B"0000";
- BEGIN
- IF CLK'EVENT AND CLK='1' THEN
- CQI := CQI + 1;
- END IF;
- CQ<=CQI;
- END PROCESS;
-END behavior;