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diff --git a/works/life/computer-organization-experiment/register.vhdl b/works/life/computer-organization-experiment/register.vhdl
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-library ieee;
-
-entity register is
- port (
- D : in std_logic_vector(31 downto 0);
- CLK, EN, CLRN: in std_logic;
- Q: out std_logic_vector(31 downto 0)
- )
-end register;
-
-architecture Behavioral of register is
-begin
- storage: process is
- begin
- if CLRN = '0' then
- Q <= H"00000000";
- elsif rising_edge(CLK) and EN = '1' then
- Q <= D;
- end if;
- end process;
-end Behavioral;