1 files changed, 44 insertions, 25 deletions
diff --git a/works/life/computer-organization-experiment/test_bench.vhdl b/works/life/computer-organization-experiment/test_bench.vhdl
index be15df9..756aa8d 100644
--- a/works/life/computer-organization-experiment/test_bench.vhdl
+++ b/works/life/computer-organization-experiment/test_bench.vhdl
@@ -9,20 +9,20 @@ architecture test_counter_4 of test_bench is
   signal CLK : STD_LOGIC;
   signal CQ: STD_LOGIC_VECTOR(3 DOWNTO 0);
 begin
-    counter: entity work.counter_4(behavior)
-        port map (CLK, CQ);
-    stimulus: process is
-    begin
-      for count_value in 0 to 2 ** 4 - 1 loop
-        if count_value mod 2 = 0 then
-          CLK <= '1';
-          wait for 5 ns;
-        else
-          CLK <= '0';
-          wait for 5 ns;
-        end if;
-      end loop;
-    end process stimulus;
+  counter: entity work.counter_4(behavior)
+      port map (CLK, CQ);
+  stimulus: process is
+  begin
+    for count_value in 0 to 2 ** 4 - 1 loop
+      if count_value mod 2 = 0 then
+        CLK <= '1';
+        wait for 5 ns;
+      else
+        CLK <= '0';
+        wait for 5 ns;
+      end if;
+    end loop;
+  end process stimulus;
 end architecture test_counter_4;
 
 
@@ -31,15 +31,34 @@ architecture test_full_adder_1 of test_bench is
   signal I: v3 := B"000";
   signal S, CO : STD_LOGIC;
 begin
-    adder: entity work.full_adder_1(behavior)
-        port map (I(2), I(1), I(0), S, CO);
-    stimulus: process is
-      variable ii : v3 := B"000";
-    begin
-      loop
-        ii := ii + 1;
-        I <= ii;
-        wait for 5 ns;
-      end loop;
-    end process stimulus;
+  adder: entity work.full_adder_1(behavior)
+      port map (I(2), I(1), I(0), S, CO);
+  stimulus: process is
+    variable ii : v3 := B"000";
+  begin
+    loop
+      ii := ii + 1;
+      I <= ii;
+      wait for 5 ns;
+    end loop;
+  end process stimulus;
 end architecture test_full_adder_1;
+
+architecture test_multiplexer_32_2 of test_bench is
+  signal A0: std_logic_vector(31 downto 0) := B"11111111111111111111111111111111";
+  signal A1: std_logic_vector(31 downto 0) := B"00000000000000000000000000000000";
+  signal S: std_logic;
+  signal Y: std_logic_vector(31 downto 0);
+begin
+  multiplexer: entity work.multiplexer_32_2(behaviour)
+      port map (A0, A1, S, Y);
+  stimulus: process is
+  begin
+    loop
+      S <= '0';
+      wait for 5 ns;
+      S <= '1';
+      wait for 5 ns;
+    end loop;
+  end process stimulus;
+end architecture test_multiplexer_32_2;