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-rw-r--r--works/life/computer-organization-experiment/test_bench.vhdl20
1 files changed, 20 insertions, 0 deletions
diff --git a/works/life/computer-organization-experiment/test_bench.vhdl b/works/life/computer-organization-experiment/test_bench.vhdl
index 6e5e9e8..d2910d7 100644
--- a/works/life/computer-organization-experiment/test_bench.vhdl
+++ b/works/life/computer-organization-experiment/test_bench.vhdl
@@ -124,3 +124,23 @@ begin
end loop;
end process stimulus;
end architecture test_shift_32;
+
+
+architecture test_alu of test_bench is
+ signal A: std_logic_vector(31 downto 0) := "00000000000000000000000000000011";
+ signal B: std_logic_vector(31 downto 0) := "00000000000000000000000000000011";
+ signal S: std_logic_vector(31 downto 0);
+ signal ALUC: std_logic_vector(3 downto 0) := "0000";
+ signal Z: std_logic;
+begin
+ alu: entity work.alu(Behavioral)
+ port map (A, B, ALUC, S, Z);
+ stimulus: process is
+ begin
+ loop
+ wait for 5 ns;
+ ALUC <= ALUC + 1;
+ end loop;
+
+ end process stimulus;
+end architecture test_alu; \ No newline at end of file