blob: 1fdeb0f821f469e8b2b55305b929717a85d9b9c0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexer_1_2 is
port (A0, A1, S : in std_logic; Y: out std_logic);
end multiplexer_1_2;
architecture behaviour of multiplexer_1_2 is
begin
Y <= A0 when S = '0' else A1;
end behaviour;
|
