x86_64: fix exception stack alignment

* i386/i386/pcb.c:
  - increase alignment of pcb cache to 16
  - ensure the stack is properly aligned when switching ktss
* i386/i386/thread.h:
  - add padding tomake iss field end aligned to 16 bytes
* i386/i386/trap.c:
  - ensure the state we get after the trap points to the correct place
    in the pcb structure

When handling exceptions from IA-32e compatibility mode in user space,
on a 64-bit kernel, the exception stack where error info is pushed
needs to be aligned to 16 bytes (see Intel System Programming guide,
$6.14.2)

The exception stack frame is set in the middle of pcb->iss, but it's not always
16-byte aligned; to make sure it is, we increase the alignment of the
pcb cache and add a padding field in the pcb structure.

This issue resulted in a general protection failure due to CS being
corrupted after a page fault.  The corruption was happening when the
exception stack frame was not properly aligned and a page fault
happened; the error info was then pushed after re-aligning the stack,
so the value of eflags was actually written in CS place and other
fields were shifted too.

It also makes sense to ensure this by adding two assertions, although
these were primarly useful during debug.

Signed-off-by: Luca Dariz <luca@orpolo.org>
Message-Id: <20220628101054.446126-10-luca@orpolo.org>

0 files changed, 0 insertions, 0 deletions