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| author | Samuel Thibault <samuel.thibault@ens-lyon.org> | 2012-03-18 20:31:22 +0100 |
|---|---|---|
| committer | Samuel Thibault <samuel.thibault@ens-lyon.org> | 2020-03-28 17:01:53 +0100 |
| commit | 0b3504b6db86c531e8b53b8e9aa9030db6e72357 (patch) | |
| tree | bbdcc8907f2e1700721de715220e28773518c657 /i386/intel/pmap.h | |
| parent | e3460f05cbe141073e62c24afe5e3a8f99c05ed4 (diff) | |
| download | gnumach-0b3504b6db86c531e8b53b8e9aa9030db6e72357.tar.gz gnumach-0b3504b6db86c531e8b53b8e9aa9030db6e72357.tar.bz2 gnumach-0b3504b6db86c531e8b53b8e9aa9030db6e72357.zip | |
pmap.h: Add 64bit variant
* i386/intel/pmap.h (L4SHIFT, L4MASK, lin2l4num): New macros
(PDPNUM, PDPMASK, set_pmap): Add 64bit variant. Make PAE use the 64bit mask
too.
(pmap): Add l4base, user_l4base, user_pdpbase fields.
* i386/intel/pmap.c (pmap_bootstrap): Clear the whole PDP. Enable write
bit in PDP. Set user pagetable to NULL. Initialize l4base.
(pmap_clear_bootstrap_pagetable): Add 4th-level support.
(pmap_ceate): Clear the whole PDP. Enable write bit in PDP. Initialize
l4base, user_pdpbase, user_l4base.
(pmap_destroy): Clear l4base, user_pdpbase, user_l4base.
* i386/i386at/model_dep.c (i386at_init): Load l4base on 64bits.
Diffstat (limited to 'i386/intel/pmap.h')
| -rw-r--r-- | i386/intel/pmap.h | 41 |
1 files changed, 39 insertions, 2 deletions
diff --git a/i386/intel/pmap.h b/i386/intel/pmap.h index 5fa2a0c4..4c852543 100644 --- a/i386/intel/pmap.h +++ b/i386/intel/pmap.h @@ -48,7 +48,7 @@ * Define the generic in terms of the specific */ -#if defined(__i386__) +#if defined(__i386__) || defined(__x86_64__) #define INTEL_PGBYTES I386_PGBYTES #define INTEL_PGSHIFT I386_PGSHIFT #define intel_btop(x) i386_btop(x) @@ -71,9 +71,18 @@ typedef phys_addr_t pt_entry_t; #define INTEL_OFFMASK 0xfff /* offset within page */ #if PAE +#ifdef __x86_64__ +#define L4SHIFT 39 /* L4 shift */ +#define L4MASK 0x1ff /* mask for L4 index */ +#endif #define PDPSHIFT 30 /* page directory pointer */ +#ifdef __x86_64__ +/* Enough for 8GiB addressing space. */ +#define PDPNUM 8 /* number of page directory pointers */ +#else #define PDPNUM 4 /* number of page directory pointers */ -#define PDPMASK 3 /* mask for page directory pointer index */ +#endif +#define PDPMASK 0x1ff /* mask for page directory pointer index */ #define PDESHIFT 21 /* page descriptor shift */ #define PDEMASK 0x1ff /* mask for page descriptor index */ #define PTESHIFT 12 /* page table shift */ @@ -87,6 +96,13 @@ typedef phys_addr_t pt_entry_t; #endif /* PAE */ /* + * Convert linear offset to L4 pointer index + */ +#ifdef __x86_64__ +#define lin2l4num(a) (((a) >> L4SHIFT) & L4MASK) +#endif + +/* * Convert linear offset to page descriptor index */ #define lin2pdenum(a) (((a) >> PDESHIFT) & PDEMASK) @@ -167,6 +183,13 @@ struct pmap { #else pt_entry_t *pdpbase; /* page directory pointer table */ #endif /* ! PAE */ +#ifdef __x86_64__ + pt_entry_t *l4base; /* l4 table */ +#ifdef MACH_HYP + pt_entry_t *user_l4base; /* Userland l4 table */ + pt_entry_t *user_pdpbase; /* Userland l4 table */ +#endif /* MACH_HYP */ +#endif /* x86_64 */ int ref_count; /* reference count */ decl_simple_lock_data(,lock) /* lock on map */ @@ -187,7 +210,21 @@ extern void pmap_clear_bootstrap_pagetable(pt_entry_t *addr); #endif /* MACH_PV_PAGETABLES */ #if PAE +#ifdef __x86_64__ +#ifdef MACH_HYP +#define set_pmap(pmap) \ + MACRO_BEGIN \ + set_cr3(kvtophys((vm_offset_t)(pmap)->l4base)); \ + if (pmap->user_l4base) \ + if (!hyp_set_user_cr3(kvtophys((vm_offset_t)(pmap)->user_l4base))) \ + panic("set_user_cr3"); \ + MACRO_END +#else /* MACH_HYP */ +#define set_pmap(pmap) set_cr3(kvtophys((vm_offset_t)(pmap)->l4base)) +#endif /* MACH_HYP */ +#else /* x86_64 */ #define set_pmap(pmap) set_cr3(kvtophys((vm_offset_t)(pmap)->pdpbase)) +#endif /* x86_64 */ #else /* PAE */ #define set_pmap(pmap) set_cr3(kvtophys((vm_offset_t)(pmap)->dirbase)) #endif /* PAE */ |