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* fpu_set_state: accept fp_save_kind being incoherent if initialized is not setSamuel Thibault2024-09-081-1/+1
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* fpu_set_state: return an error on incoherent fp_save_kindSamuel Thibault2024-09-081-1/+3
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* add xfloat thread state interfaceLuca Dariz2024-09-085-43/+161
| | | | | | | | | | | | | | | | | * i386/i386/fpu.c: extend current getter and setter to support the extended state; move the struct casting here to reuse the locking and allocation logic for the thread state; make sure the new state is set as valid, otherwise it won't be applied; add i386_get_xstate_size() to dynamically retrieve the FPU state size. * i386/i386/fpu.h: update prototypes to accept generic thread state * i386/i386/pcb.c: forward raw thread state to getter and setter, only checking for minimum size and use the new i386_get_xstate_size() helper. * i386/include/mach/i386/mach_i386.defs: expose the new helper i386_get_xstate_size(). * i386/include/mach/i386/thread_status.h: add interface definition for I386_XFLOAT_STATE and the corresponding data structure. Message-ID: <20240904201806.510082-1-luca@orpolo.org>
* fpu: Drop conflicting alignmentSamuel Thibault2024-07-311-1/+1
| | | | | struct i386_xfp_xstate_header header is at offset 440 of struct i386_xfp_save, so not a multiple of 64 anyway.
* Fix xen buildSamuel Thibault2024-07-071-0/+2
| | | | | with -Werror=incompatible-pointer-types and -Werror=implicit-function-declaration.
* SMP: force APICSamuel Thibault2024-04-051-0/+6
| | | | We need it to properly driver interrupts etc. of APs
* kd: Include i386/irq.hSamuel Thibault2024-03-271-0/+1
| | | | to get unmask_irq declaration
* Make -fno-PIE etc. architecture-dependentSergey Bugaev2024-03-271-0/+4
| | | | | | | | | | There might be good reasons why Mach on x86 shouldn't be built as PIC/ PIE, but there are also very good reasons to support PIE on other architectures. Potentially implementing KASLR is one such reason; but also the Linux AArch64 boot protocol (that the AArch64 port will use for booting) lets the bootloader load the kernel image at any address, which makes PIC pretty much required. Message-ID: <20240327161841.95685-11-bugaevc@gmail.com>
* x86_64: avoid iterating over the message twice in copyoutmsg/copyinmsg for ↵Flavio Cruz2024-03-111-0/+6
| | | | | | | | | | | | | | | | faster RPCs. This is a follow up to https://git.savannah.gnu.org/cgit/hurd/gnumach.git/commit/?id=69620634858b2992e1a362e33c95d9a8ee57bce7 where we made inlined ports 8 bytes long to avoid resizing. The last thing that copy{in,out}msg were doing was just updating msgt_size field since that's required for kernel stub code and implicitly assumed by IPC code. This was moved into ipc_kmsg_copy{in,out}_body. For a 32 bit userland, the code also stops updating msgt_size for out of line ports, same as the 64 bit userland. Message-ID: <ZdQxWNSieTHcpM1b@jupiter.tail36e24.ts.net>
* move x86 copy_user.[ch] to ipc/ and make it arch-indipendentLD2024-03-092-101/+0
| | | | Message-ID: <20240309140244.347835-3-luca@orpolo.org>
* remove machine/machspl.h as it duplicates machine/spl.hLD2024-03-0915-43/+13
| | | | Message-ID: <20240309140244.347835-2-luca@orpolo.org>
* pmap: Avoid leaking USER bit in page tablesSamuel Thibault2024-03-031-5/+6
| | | | | | | | | | We should only set USER - for user processes maps - for 32bit Xen support This was not actually posing problem since in 32bit segmentation protects us, and in 64bit the l4 entry for the kernel is already set. But better be safe than sorry.
* kernel traps: also catch general protection faultsSamuel Thibault2024-03-031-0/+3
| | | | | | If userland passes a kernel pointer, it's not a page fault that we get, but a general protection fault. We also want to go through the recovery in that case, to make e.g. copyin/out return an error.
* spl: Introduce assert_splvm and use it in process_pmap_updatesSamuel Thibault2024-02-232-0/+2
| | | | Suggested-by: Damien Zammit <damien@zamaudio.com>
* vm_map_lookup: Add parameter for keeping map lockedDamien Zammit2024-02-221-2/+2
| | | | | | | | | | | This adds a parameter called keep_map_locked to vm_map_lookup() that allows the function to return with the map locked. This is to prepare for fixing a bug with gsync where the map is locked twice by mistake. Co-Authored-By: Sergey Bugaev <bugaevc@gmail.com> Message-ID: <20240222082410.422869-3-damien@zamaudio.com>
* Introduce and use assert_splsched()Samuel Thibault2024-02-191-0/+1
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* process_pmap_updates: Use _nocheck form of lock, already at splvmDamien Zammit2024-02-191-2/+5
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* locore: Remove unnecessary call to CPU_NUMBERDamien Zammit2024-02-181-2/+1
| | | | The cpu number is already in edx register, so use that.
* Replace kernel header includes in include/mach/mach_types.h with forward ↵Flavio Cruz2024-02-124-1/+4
| | | | | | | | | | | | | | | declarations. I was trying to reuse TASK_NAME_SIZE in kern/thread.h but it was impossible because files included from kern/task.h end up requiring kern/thread.h (through percpu.h), creating a recursive dependency. With this change, mach_types.h only defines forward declarations and modules have to explicitly include the appropriate header file if they want to be able touch those structures. Most of the other includes are required because we no longer grab many different includes through mach_types.h. Message-ID: <20240212062634.1082207-1-flaviocruz@gmail.com>
* smp: Fix unable to enter kdb during bootDamien Zammit2024-02-112-2/+1
| | | | Message-ID: <20240211115958.1889648-1-damien@zamaudio.com>
* Fix build with APIC without SMPSamuel Thibault2024-02-102-1/+3
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* smp: Fix compile error with missing apboot_addrDamien Zammit2024-02-092-5/+5
| | | | Message-ID: <20240209021108.1715770-1-damien@zamaudio.com>
* smp: Fix INIT/STARTUP IPI sequenceDamien Zammit2024-02-094-40/+110
| | | | | | TESTED: works in qemu TESTED: works hardware with AMD cpu Message-ID: <20240207050158.1640853-5-damien@zamaudio.com>
* SMP: Fix allocating the apboot pageSamuel Thibault2024-02-092-8/+9
| | | | | vm_page_grab_contig does not necessarily allocate at the beginning of the DMA segment, so rather allocate by hand very early.
* fpu: Fix cpuid feature detectionOlivier Valentin2024-02-081-3/+8
| | | | | Make sure to fetch capabilities from cpuid(0xd,0x1) Message-ID: <20240208165015.4700-3-valentio@free.fr>
* Revert "fpu: Fix cpuid feature detection"Olivier Valentin2024-02-081-15/+25
| | | | | This reverts commit f8d0f98e80b3d7d9b24fa077818113fb0f4b3970. Message-ID: <20240208165015.4700-2-valentio@free.fr>
* smp: Use HPET instead of pit one-shot that is unreliableDamien Zammit2024-02-081-4/+3
| | | | | | | NB: Every x86 board that uses ACPI most likely has a HPET since 2005. We can roll back to PIT in the cases where its not present, but the PIT one shot code is definitely currently broken. Message-ID: <20240207050158.1640853-4-damien@zamaudio.com>
* Add HPET timer for small accurate delaysDamien Zammit2024-02-085-8/+150
| | | | | | | TESTED: This works in qemu correctly TESTED: This works on an AMD board with ACPI v2.0 correctly Message-ID: <20240207050158.1640853-3-damien@zamaudio.com>
* separate lapic_enable from lapic_setupDamien Zammit2024-02-084-5/+31
| | | | | | | This initializes the lapic without turning on the IOAPIC interrupts during SMP init. Message-ID: <20240207050158.1640853-2-damien@zamaudio.com>
* apboot: avoid self-modifying codeSamuel Thibault2024-02-052-15/+10
| | | | | | self-modifying code is generally frowned upon, Intel largely says the support is model-dependent. We can as well just relocate from the C code like we did for the temporary gdt.
* smp: Remove hardcoded AP_BOOT_ADDRDamien Zammit2024-02-054-11/+55
| | | | | | | | | | | | | This took some time to figure out. Involves a hand-crafted 16 bit assembly instruction [1] because it requires an immediate for the memory address of far jump. This required self-modifying code to inject the next instruction, therefore I added a near jump to clear the instruction cache queue in case the pipeline cached the unmodified jump location. [1] Intel Architecture Software Developer's Manual, Volume 2: Instruction Set Reference Manual
* Fix apic_send_ipi function clobbering read only fieldsDamien Zammit2024-02-052-3/+7
| | | | | | | | | This was the root cause of failing to INIT. We were clobbering remote_read_status. And also, we need to reference the .r register when writing the ICR regs otherwise I think it writes all of the block. Message-ID: <20240205113327.1568218-2-damien@zamaudio.com>
* ACPI: Support XSDT (ACPI >= v2.0)Damien Zammit2024-02-013-89/+195
| | | | | | | | | This enables gnumach to additionally parse the XSDT table if the revision of ACPI is 2. TESTED: Still works on qemu (ACPI v1.0) TESTED: Works on a x86 board with XSDT (ACPI v2.0) Message-ID: <20240131021218.1335821-1-damien@zamaudio.com>
* model_dep: Fix serial console with APIC enabledDamien Zammit2024-02-011-5/+5
| | | | | | | Move cninit() further down so that IOAPIC has a chance to initialize before the com port interrupt is unmasked in the IOAPIC, fixing a fault and reboot. Message-ID: <20240131100210.1354522-1-damien@zamaudio.com>
* Add vm_pages_physSamuel Thibault2024-01-302-0/+2
| | | | | | | | For rumpdisk to efficiently determine the physical address, both for checking whether it is below 4GiB, and for giving it to the disk driver, we need a gnumach primitive (and that is not conditioned by MACH_VM_DEBUG like mach_vm_region_info and mach_vm_object_pages_phys are).
* apic: Set up LAPICs in xAPIC modeDamien Zammit2024-01-303-4/+6
| | | | | | Clear flag in msr for xAPIC mode. Message-ID: <20240130080405.1304381-1-damien@zamaudio.com>
* Support up to two IOAPICs with up to 32 GSIs on eachDamien Zammit2024-01-296-7/+153
| | | | | | | Previously, only IOAPIC[0] was supported. Now this supports up to two IOAPICs. Message-ID: <20240129100652.1262126-1-damien@zamaudio.com>
* fpu: Fix cpuid feature detectionOlivier Valentin2024-01-271-25/+15
| | | | | | Make sure to fetch capabilities from cpuid(0xd,0x1) and max structure sizes from cpuid(0xd,0x0). Message-ID: <20240124080019.8136-1-valentio@free.fr>
* ioapic: Remove IMCR toggleDamien Zammit2024-01-271-6/+0
| | | | | | | | Since we are not using legacy MP tables but intending to use ACPI to configure interrupt routing, we can assume all boards have virtual wire mode, thus do not require setting of IMCR register. (This may fix crashes on machines that do not have IMCR registers). Message-ID: <20240124035138.1044855-2-damien@zamaudio.com>
* console: Fix baud rate on com ports, use 115200 default baud, 8 data bitsDamien Zammit2024-01-202-16/+5
| | | | | | | | TESTED: By booting gnumach off an HP T620 with console=com0 and receiving 115200 8N1 console on another machine connected via the serial port in minicom. Without this patch, part of the console is garbled by mismatching com params (9600 7N1). Message-ID: <20240119031214.691086-1-damien@zamaudio.com>
* x86_64: Support 8 byte inlined port rights to avoid message resizing.Flavio Cruz2023-12-171-7/+5
| | | | | | | | | | If a port is inlined in a message, the user has to use mach_port_name_inlined_t to define each port. Out of line memory continues to use mach_port_name_t since that memory has to be copied to the kernel anyway. Both copyinmsg and copyoutmsg can be reduced to nothing (if we ignore USER32) as a follow up but kept this patch simple for ease of review.
* Revert "x86_64: Support 8 byte inlined port rights to avoid message resizing."Samuel Thibault2023-12-031-5/+7
| | | | This reverts commit 29d4bcaafc4c2040df27a6247603c68e7757205c.
* Xen: fix buildSamuel Thibault2023-12-033-2/+6
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* x86_64: Support 8 byte inlined port rights to avoid message resizing.Flavio Cruz2023-12-031-7/+5
| | | | | | | | | | | If a port is inlined in a message, the user has to use mach_port_name_inlined_t to define each port. Out of line memory continues to use mach_port_name_t since that memory has to be copied to the kernel anyway. Both copyinmsg and copyoutmsg can be reduced to nothing (if we ignore USER32) as a follow up but kept this patch simple for ease of review. Message-ID: <ZWg00XzFPqqL1yF-@jupiter.tail36e24.ts.net>
* locore: Homogeneize 32bit and 64bitSamuel Thibault2023-10-281-1/+1
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* 64bit: Fix locore buildSamuel Thibault2023-10-281-1/+22
| | | | | | | | | To allow references to int_stack_base to be quite unconstrained, we need to use 64bit register indexing. CPU_NUMBER_NO_GS was missing a 64bit variant. CPU_NUMBER_NO_STACK assumes being passed a 32bit register.
* 64bit: Fix types in lock.hSamuel Thibault2023-10-281-8/+8
| | | | simple locks use natural_t, and indexes for bt/bts/btr have to be 32bit.
* Factorize more push/pop codeSamuel Thibault2023-10-271-11/+25
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* locore: Also factorize segment management on i386Samuel Thibault2023-10-271-72/+52
| | | | | | and harmonize i386/x86_64. This btw fixes not using dx in 32-on-64's alltraps.
* Fix interrupt handlingDamien Zammit2023-10-031-15/+13
| | | | | | | | | | | | | | | | | | | | | | | | | Logic for interrupts: - interrupt.S raises spl (thus IF cleared) - interrupt.S EOI - interrupt.S calls the handler - for pure in-kernel handlers, they do whatever they want with IF cleared. - when a userland handler is registers, queue_intr masks the irq. - interrupt.S lowers spl with splx_cli, thus IF still cleared - iret, that sets IF - later on, userland acks the IRQ, that unmasks the irq The key to this change is that all interrupts, including IPIs, are treated the same way. Eg. the spl level is now raised before an IPI and restored after. Also, EOI is not needed inside irq_acknowledge. With this change and the experimental change not to dispatch threads direct to idle processors in the scheduler, I no longer observe kernel faults, but an occasional hang does occur. Message-Id: <20231002033906.124427-1-damien@zamaudio.com>
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