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| author | Boyuan Yang <byang@debian.org> | 2021-11-07 08:50:18 -0500 |
|---|---|---|
| committer | Boyuan Yang <byang@debian.org> | 2021-11-07 08:50:18 -0500 |
| commit | 320ef65362608ee1148c299d8d5d7618af34e470 (patch) | |
| tree | c47911c219d1e35b8b0771e9e0176eff0e0d08ec /src/dsp/x86/inverse_transform_sse4.h | |
| parent | 2381d803c76105f44717d75f089ec37f51e5cfe4 (diff) | |
| download | libgav1-320ef65362608ee1148c299d8d5d7618af34e470.tar.gz libgav1-320ef65362608ee1148c299d8d5d7618af34e470.tar.bz2 libgav1-320ef65362608ee1148c299d8d5d7618af34e470.zip | |
New upstream version 0.17.0
Diffstat (limited to 'src/dsp/x86/inverse_transform_sse4.h')
| -rw-r--r-- | src/dsp/x86/inverse_transform_sse4.h | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/src/dsp/x86/inverse_transform_sse4.h b/src/dsp/x86/inverse_transform_sse4.h index 106084b..c31e88b 100644 --- a/src/dsp/x86/inverse_transform_sse4.h +++ b/src/dsp/x86/inverse_transform_sse4.h @@ -34,56 +34,56 @@ void InverseTransformInit_SSE4_1(); // optimization being enabled, signal the sse4 implementation should be used. #if LIBGAV1_TARGETING_SSE4_1 -#ifndef LIBGAV1_Dsp8bpp_1DTransformSize4_1DTransformDct -#define LIBGAV1_Dsp8bpp_1DTransformSize4_1DTransformDct LIBGAV1_CPU_SSE4_1 +#ifndef LIBGAV1_Dsp8bpp_Transform1dSize4_Transform1dDct +#define LIBGAV1_Dsp8bpp_Transform1dSize4_Transform1dDct LIBGAV1_CPU_SSE4_1 #endif -#ifndef LIBGAV1_Dsp8bpp_1DTransformSize8_1DTransformDct -#define LIBGAV1_Dsp8bpp_1DTransformSize8_1DTransformDct LIBGAV1_CPU_SSE4_1 +#ifndef LIBGAV1_Dsp8bpp_Transform1dSize8_Transform1dDct +#define LIBGAV1_Dsp8bpp_Transform1dSize8_Transform1dDct LIBGAV1_CPU_SSE4_1 #endif -#ifndef LIBGAV1_Dsp8bpp_1DTransformSize16_1DTransformDct -#define LIBGAV1_Dsp8bpp_1DTransformSize16_1DTransformDct LIBGAV1_CPU_SSE4_1 +#ifndef LIBGAV1_Dsp8bpp_Transform1dSize16_Transform1dDct +#define LIBGAV1_Dsp8bpp_Transform1dSize16_Transform1dDct LIBGAV1_CPU_SSE4_1 #endif -#ifndef LIBGAV1_Dsp8bpp_1DTransformSize32_1DTransformDct -#define LIBGAV1_Dsp8bpp_1DTransformSize32_1DTransformDct LIBGAV1_CPU_SSE4_1 +#ifndef LIBGAV1_Dsp8bpp_Transform1dSize32_Transform1dDct +#define LIBGAV1_Dsp8bpp_Transform1dSize32_Transform1dDct LIBGAV1_CPU_SSE4_1 #endif -#ifndef LIBGAV1_Dsp8bpp_1DTransformSize64_1DTransformDct -#define LIBGAV1_Dsp8bpp_1DTransformSize64_1DTransformDct LIBGAV1_CPU_SSE4_1 +#ifndef LIBGAV1_Dsp8bpp_Transform1dSize64_Transform1dDct +#define LIBGAV1_Dsp8bpp_Transform1dSize64_Transform1dDct LIBGAV1_CPU_SSE4_1 #endif -#ifndef LIBGAV1_Dsp8bpp_1DTransformSize4_1DTransformAdst -#define LIBGAV1_Dsp8bpp_1DTransformSize4_1DTransformAdst LIBGAV1_CPU_SSE4_1 +#ifndef LIBGAV1_Dsp8bpp_Transform1dSize4_Transform1dAdst +#define LIBGAV1_Dsp8bpp_Transform1dSize4_Transform1dAdst LIBGAV1_CPU_SSE4_1 #endif -#ifndef LIBGAV1_Dsp8bpp_1DTransformSize8_1DTransformAdst -#define LIBGAV1_Dsp8bpp_1DTransformSize8_1DTransformAdst LIBGAV1_CPU_SSE4_1 +#ifndef LIBGAV1_Dsp8bpp_Transform1dSize8_Transform1dAdst +#define LIBGAV1_Dsp8bpp_Transform1dSize8_Transform1dAdst LIBGAV1_CPU_SSE4_1 #endif -#ifndef LIBGAV1_Dsp8bpp_1DTransformSize16_1DTransformAdst -#define LIBGAV1_Dsp8bpp_1DTransformSize16_1DTransformAdst LIBGAV1_CPU_SSE4_1 +#ifndef LIBGAV1_Dsp8bpp_Transform1dSize16_Transform1dAdst +#define LIBGAV1_Dsp8bpp_Transform1dSize16_Transform1dAdst LIBGAV1_CPU_SSE4_1 #endif -#ifndef LIBGAV1_Dsp8bpp_1DTransformSize4_1DTransformIdentity -#define LIBGAV1_Dsp8bpp_1DTransformSize4_1DTransformIdentity LIBGAV1_CPU_SSE4_1 +#ifndef LIBGAV1_Dsp8bpp_Transform1dSize4_Transform1dIdentity +#define LIBGAV1_Dsp8bpp_Transform1dSize4_Transform1dIdentity LIBGAV1_CPU_SSE4_1 #endif -#ifndef LIBGAV1_Dsp8bpp_1DTransformSize8_1DTransformIdentity -#define LIBGAV1_Dsp8bpp_1DTransformSize8_1DTransformIdentity LIBGAV1_CPU_SSE4_1 +#ifndef LIBGAV1_Dsp8bpp_Transform1dSize8_Transform1dIdentity +#define LIBGAV1_Dsp8bpp_Transform1dSize8_Transform1dIdentity LIBGAV1_CPU_SSE4_1 #endif -#ifndef LIBGAV1_Dsp8bpp_1DTransformSize16_1DTransformIdentity -#define LIBGAV1_Dsp8bpp_1DTransformSize16_1DTransformIdentity LIBGAV1_CPU_SSE4_1 +#ifndef LIBGAV1_Dsp8bpp_Transform1dSize16_Transform1dIdentity +#define LIBGAV1_Dsp8bpp_Transform1dSize16_Transform1dIdentity LIBGAV1_CPU_SSE4_1 #endif -#ifndef LIBGAV1_Dsp8bpp_1DTransformSize32_1DTransformIdentity -#define LIBGAV1_Dsp8bpp_1DTransformSize32_1DTransformIdentity LIBGAV1_CPU_SSE4_1 +#ifndef LIBGAV1_Dsp8bpp_Transform1dSize32_Transform1dIdentity +#define LIBGAV1_Dsp8bpp_Transform1dSize32_Transform1dIdentity LIBGAV1_CPU_SSE4_1 #endif -#ifndef LIBGAV1_Dsp8bpp_1DTransformSize4_1DTransformWht -#define LIBGAV1_Dsp8bpp_1DTransformSize4_1DTransformWht LIBGAV1_CPU_SSE4_1 +#ifndef LIBGAV1_Dsp8bpp_Transform1dSize4_Transform1dWht +#define LIBGAV1_Dsp8bpp_Transform1dSize4_Transform1dWht LIBGAV1_CPU_SSE4_1 #endif #endif // LIBGAV1_TARGETING_SSE4_1 #endif // LIBGAV1_SRC_DSP_X86_INVERSE_TRANSFORM_SSE4_H_ |