import(life): ...

3 files changed, 46 insertions, 1 deletions

diff --git a/works/life/computer-organization-experiment/Makefile b/works/life/computer-organization-experiment/Makefile
index 8777267..215a4e5 100644
--- a/works/life/computer-organization-experiment/Makefile
+++ b/works/life/computer-organization-experiment/Makefile
@@ -12,6 +12,9 @@ build/adder_8.o: build adder_8.vhdl
 build/adder_32.o: build adder_32.vhdl
 	ghdl analyze --std=08 --workdir=build -fsynopsys adder_32.vhdl
 
+build/alu.o: build alu.vhdl
+	ghdl analyze --std=08 --workdir=build -fsynopsys alu.vhdl
+
 build/counter_4.o: build counter_4.vhdl
 	ghdl analyze --std=08 --workdir=build -fsynopsys counter_4.vhdl
 
@@ -30,7 +33,7 @@ build/multiplexer_32_2.o: build multiplexer_32_2.vhdl
 build/shift_32.o: build shift_32.vhdl
 	ghdl analyze --std=08 --workdir=build -fsynopsys shift_32.vhdl
 
-build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o build/multiplexer_1_2.o build/multiplexer_8_2.o build/multiplexer_32_2.o build/adder_1.o build/adder_8.o build/adder_32.o build/shift_32.o
+build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o build/multiplexer_1_2.o build/multiplexer_8_2.o build/multiplexer_32_2.o build/adder_1.o build/adder_8.o build/adder_32.o build/shift_32.o build/alu.o
 	ghdl analyze --std=08 --workdir=build -fsynopsys test_bench.vhdl
 
 build/test_bench: build/test_bench.o
diff --git a/works/life/computer-organization-experiment/alu.vhdl b/works/life/computer-organization-experiment/alu.vhdl
new file mode 100644
index 0000000..0bb743c
--- /dev/null
+++ b/works/life/computer-organization-experiment/alu.vhdl
@@ -0,0 +1,22 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+entity alu is
+    port (A, B: in std_logic_vector(31 downto 0); ALUC: in std_logic_vector(3 downto 0); S: out std_logic_vector(31 downto 0); Z: out std_logic);
+end entity;
+
+architecture Behavioral of alu is
+begin
+    S <= A + B when ALUC(2 downto 0) = B"000"
+         else A and B when ALUC(2 downto 0) ?= B"001"
+         else A - B when ALUC(2 downto 0) ?= B"100"
+         else A or B when ALUC(2 downto 0) ?= B"101"
+         else A xor B when ALUC(2 downto 0) ?= B"010"
+         else std_logic_vector(signed(A) sll 16) and B"11111111111111110000000000000000" when ALUC(2 downto 0) ?= B"110"
+         else std_logic_vector(signed(A) sll to_integer(unsigned(B))) when ALUC ?= B"0011"
+         else std_logic_vector(signed(A) srl to_integer(unsigned(B))) when ALUC ?= B"0111"
+         else std_logic_vector(signed(A) sra to_integer(unsigned(B))) when ALUC ?= B"1111";
+    Z <= S ?= "00000000000000000000000000000000";
+end architecture;
diff --git a/works/life/computer-organization-experiment/test_bench.vhdl b/works/life/computer-organization-experiment/test_bench.vhdl
index 6e5e9e8..d2910d7 100644
--- a/works/life/computer-organization-experiment/test_bench.vhdl
+++ b/works/life/computer-organization-experiment/test_bench.vhdl
@@ -124,3 +124,23 @@ begin
     end loop;
   end process stimulus;
 end architecture test_shift_32;
+
+
+architecture test_alu of test_bench is
+ signal A: std_logic_vector(31 downto 0) := "00000000000000000000000000000011";
+ signal B: std_logic_vector(31 downto 0) := "00000000000000000000000000000011";
+ signal S: std_logic_vector(31 downto 0);
+ signal ALUC: std_logic_vector(3 downto 0) := "0000";
+ signal Z: std_logic;
+begin
+  alu: entity work.alu(Behavioral)
+      port map (A, B, ALUC, S, Z);
+  stimulus: process is
+  begin
+    loop
+      wait for 5 ns;
+      ALUC <= ALUC + 1;
+    end loop;
+    
+  end process stimulus;
+end architecture test_alu;
\ No newline at end of file