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* add setting gs/fsbaseLuca Dariz2023-05-013-3/+42
| | | | | | | | | | | * i386/i386/i386asm.sym: add offsets for asm * i386/i386/pcb.c: switch FSBASE/GSBASE on context switch and implement accessors in thread setstatus/getstatus * i386/i386/thread.h: add new state to thread saved state * kern/thread.c: add i386_FSGS_BASE_STATE handler * x86_64/locore.S: fix fs/gs handling, skipping the base address and avoid resetting it by manually re-loading fs/gs Message-Id: <20230419194703.410575-5-luca@orpolo.org>
* x86_64: add 64-bit syscall entry pointLuca Dariz2023-05-016-14/+95
| | | | | | | | | | | | | | | | | | | | | | | | | While theoretically we could still use the same call gate as for 32-bit userspace, it doesn't seem very common, and gcc seems to not encode properly the instruction. Instead we use syscall/sysret as other kernels (e.g. XNU,Linux). This version still has some limitations, but should be enough to start working on the 64-bit user space. * i386/i386/i386asm.sym: add more constants to fill pcb->iss * i386/i386/ldt.c: configure 64-bit syscall entry point. We can just check for the SEP bit as MSR are always available on x86_64. * i386/i386/ldt.h: swap CS/DS segments order if !USER32 as required by sysret * i386/i386/locore.h: add syscall64 prototype * i386/i386/msr.h: add MSR definitions and C read/write helpers * i386/include/mach/i386/syscall_sw.h: remove old BSD_TRAP * x86_64/Makefrag.am: selectively install syscall_sw.h depending on USER32 * x86_64/include/syscall_sw.h: add entry point template from user space * x86_64/locore.S: implement syscall64 entry point and use it when a 64-bit user-space is configured Message-Id: <20230419194703.410575-4-luca@orpolo.org>
* Fix Xen buildSamuel Thibault2023-04-113-30/+32
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* Fix missing shipping required headerSamuel Thibault2023-04-101-0/+1
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* Align the user stack correctly for 64 bit programs.Flavio Cruz2023-04-042-8/+18
| | | | | | | | | | | * i386/i386/thread.h: Define USER_STACK_ALIGN which is 16-byte for 64 bit programs as recommended by the System V AMD64 guidelines. Also define KERNEL_STACK_ALIGN which can differ from user land. * i386/i386/pcb.c: Use USER_STACK_ALIGN to align the bootstrap arguments and ultimately the stack where the program starts on. * kern/bootstrap.c: Do not align arg_len here since it will be aligned in set_user_regs. Message-Id: <ZCpOb6vNEfPclKPr@jupiter.tail36e24.ts.net>
* Make exception subcode a longSergey Bugaev2023-04-032-2/+2
| | | | | | | | | On EXC_BAD_ACCESS, exception subcode is used to pass the faulting memory address, so it needs to be (at least) pointer-sized. Thus, make it into a long. This requires matching changes in glibc and the Hurd. Message-Id: <20230319151017.531737-4-bugaevc@gmail.com>
* Add i386_fsgs_base_stateSergey Bugaev2023-04-031-0/+8
| | | | Message-Id: <20230319151017.531737-2-bugaevc@gmail.com>
* ioapic: Timer calibrated in 10 mach ticksDamien Zammit2023-03-111-5/+4
| | | | | | | | hz variable is the number of mach ticks in 1 second. We want to know how many lapic ticks in 1 mach tick. Therefore, we set a timer for 10 mach ticks and divide the lapic stopwatch counter value by 10. Message-Id: <20230311072937.450161-1-damien@zamaudio.com>
* Align mach_msg_type_t and mach_msg_type_long_t with the same alignment as ↵Flavio Cruz2023-03-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | uintptr_t. With this change, any 64 bit code using the IPC subsystem without relying on MiG will work without any changes. We have a few examples of this inside gnumach but also in the Hurd servers. For example, in hurd/console/display.c typedef struct { mach_msg_header_t Head; mach_msg_type_t ticknoType; natural_t tickno; mach_msg_type_t changeType; file_changed_type_t change; mach_msg_type_t startType; loff_t start; mach_msg_type_t endType; loff_t end; } Request; This will now work correctly in 64 bits, without requiring any explicit padding. As a follow up, we can simplify mach_msg_type_long_t so that we only need an 8 byte structure where the second field will include the number of elements for the long form. This is already included in mach_msg_type_t as unused_msgtl_number. Message-Id: <ZAbhOfOzsb8qPFs6@jupiter.tail36e24.ts.net>
* kern: Fix MACH_LOCK_MON lock monitoring debugDamien Zammit2023-03-071-3/+3
| | | | | | | | TESTED: - by setting MACH_LOCK_MON to 1 in configfrag.ac and running "show all slocks" in kdb - does not break default configured kernel Message-Id: <20230306070512.292715-1-damien@zamaudio.com>
* apic: Drop declaration of inexisting functionSamuel Thibault2023-03-071-1/+0
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* lapic timer: Calibrate via mach timer not PITDamien Zammit2023-03-073-38/+54
| | | | | | | | | | | Previously the lapic timer was calibrated by one-shot PIT timer2. This method can be buggy and generally unused in emulation environments. This patch reworks the timer calibration to use a mach timer based on regular PIT interrupts to remapped IOAPIC pin. This also changes the primary clock source to use PIT timer0 remapped to an IOAPIC pin when APIC mode is enabled, instead of a periodic lapic timer. Message-Id: <20230306070452.292697-1-damien@zamaudio.com>
* x86_64: fix user trap during syscall with an invalid user stackLuca Dariz2023-02-271-2/+2
| | | | | | | * i386/i386/locore.h: user vm_offset_t in the recovery_table * x86_64/locore.S: fix RECOVERY() location and keep user regs in %rbx, as it seems the convention. This only applies to 32-bit userspace. Message-Id: <20230227204501.2492152-5-luca@orpolo.org>
* x86_64: allow compilation if ! USER32Luca Dariz2023-02-271-2/+4
| | | | | | * i386/intel/pmap.c: remove #error and allow compilation, keeping a reminder to fix the pmap module. Message-Id: <20230227204501.2492152-2-luca@orpolo.org>
* lapic timer: Calibrate based on 10 PIT sleeps for 10msDamien Zammit2023-02-261-8/+11
| | | | | | NB: This relies on a fix for QEMU as one-shot PIT mode is currently broken in qemu. Message-Id: <20230226013110.50606-1-damien@zamaudio.com>
* pit: Use corrected clock frequencyDamien Zammit2023-02-261-1/+1
| | | | | | All PC compatibles operate the PIT at a clock rate of (105/88) MHz Message-Id: <20230226063555.66284-1-damien@zamaudio.com>
* pit: Fix shadowed hz variable && define modes correctlyDamien Zammit2023-02-262-8/+9
| | | | Message-Id: <20230226013052.50577-1-damien@zamaudio.com>
* kd_mouse: Fix IBM mouse irq getting stuck and blocking consoleDamien Zammit2023-02-251-2/+5
| | | | | | TESTED: With and without apic/smp Message-Id: <20230225061420.16985-1-damien@zamaudio.com>
* model_dep: Call acpi_apic_init if APIC definedDamien Zammit2023-02-191-2/+3
| | | | | | | | | | | Fixes boot --enable-ncpus=1 with --enable-apic configuration albeit the keyboard is stuck and network cannot be accessed. Error messages: Timeout reached while wating for return value /bin/console: Could not receive return value from daemon process: Connection timed out Message-Id: <20230219022351.25767-1-damien@zamaudio.com>
* x86_64: set user segments as 64-bit if ! USER32Luca Dariz2023-02-161-2/+8
| | | | | * i386/i386/ldt.c: set the L bit if user-space is 64-bit Message-Id: <20230216213318.2048699-4-luca@orpolo.org>
* x86_64: load Elf64 bootstrap modules if ! USER32Luca Dariz2023-02-161-1/+19
| | | | | | | | | * i386/include/mach/i386/exec/elf.h: add Elf64 definitions and define common Elf structures, corresponding to 32/64 bit variants at compile time. * include/mach/exec/elf.h: add Elf64 definitions * kern/elf-load.c: use common Elf structures Message-Id: <20230216213318.2048699-2-luca@orpolo.org>
* x86_64: fix some compiler warningsLuca Dariz2023-02-162-7/+5
| | | | | | | * i386/include/mach/i386/vm_param.h: extend the vm constants to ULL on x86_64 to avoid a shift overflow warning * i386/intel/pmap.c: fix cast and unused variables Message-Id: <20230216213318.2048699-1-luca@orpolo.org>
* trap: Fix Wformat issuesDamien Zammit2023-02-161-5/+5
| | | | Message-Id: <20230216070205.1243532-1-damien@zamaudio.com>
* Rename efl to rfl for x86_64 in struct i386_thread_stateFlavio Cruz2023-02-152-6/+9
| | | | Message-Id: <Y+xwZ63X1PHDJwTX@jupiter.tail36e24.ts.net>
* pmap: Make mapwindow per CPUSamuel Thibault2023-02-152-12/+8
| | | | | | They are used temporarily without CPU exchanges, and may need to be used concurrently so 2 slots only would not be enough anyway. This also saves having to lock for them.
* Add missing init_fpu() for APsDamien Zammit2023-02-151-0/+2
| | | | Message-Id: <20230215095706.1213703-2-damien@zamaudio.com>
* smp: Fix more busy loopsSamuel Thibault2023-02-152-3/+4
| | | | | We need to avoid the kernel optimizing away the reads from memory. Use a standard relaxing instruction for that.
* pmap: Do not TLB shootdown IPI for mapwindow updatesSamuel Thibault2023-02-151-1/+2
| | | | | | These are used only temporarily by the current processor only, so we don't need to notify other processors about them. We however then should flush TLB at allocation, to make sure we don't have some remnant.
* pmap: Fix busy loop waiting for pmap usersSamuel Thibault2023-02-155-12/+12
| | | | | We need to avoid the kernel optimizing away the read from pmap->cpus_using. Use a standard relaxing instruction for that.
* pmap: Do not send TLB flush IPI when a cpu is idleSamuel Thibault2023-02-152-1/+3
| | | | | | | MARK_CPU_ACTIVE already knows to flush TLB when a cpu comes out of idle. However, add memory barriers to be sure that setting cpu_update_needed is seen before testing for cpus_idle.
* Fix warningSamuel Thibault2023-02-141-2/+2
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* Remove verbose debug printfsDamien Zammit2023-02-143-3/+0
| | | | Message-Id: <20230213084919.1157074-5-damien@zamaudio.com>
* Make curr_ipl[] per cpuDamien Zammit2023-02-146-29/+37
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* pmap: Signal cpu for TLB update if kernel_pmapDamien Zammit2023-02-131-1/+1
| | | | Message-Id: <20230213084919.1157074-3-damien@zamaudio.com>
* interrupt.S: Dont change ipl for pmap_update_interruptDamien Zammit2023-02-131-3/+3
| | | | Message-Id: <20230213084919.1157074-2-damien@zamaudio.com>
* cpu_number: Short circuit if smp init not doneDamien Zammit2023-02-132-0/+7
| | | | | | | This depends on serialised AP init patch. Fixes warnings spewing at boot with APIC and SMP Message-Id: <20230204101529.877846-1-damien@zamaudio.com>
* mp_desc: Add missing setting PAE mode on APSamuel Thibault2023-02-131-0/+3
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* i386: Refactor int stacks to be per cpu for SMPDamien Zammit2023-02-135-92/+201
| | | | | | | This also serialises the AP bringup, so paging can be enabled per cpu one by one. Also-by: Almudena Garcia <liberamenso10000@gmail.com>
* Add x86_64 registers to i386_thread_stateFlavio Cruz2023-02-122-2/+71
| | | | | This is required to implement ptrace. Message-Id: <Y+kvVSoC+5bvsazl@jupiter.tail36e24.ts.net>
* move kernel virtual address space to upper addressesLuca Dariz2023-02-124-9/+27
| | | | | | | | | | | | | | | | | | * i386/i386/vm_param.h: adjust constants to the new kernel map - the boothdr.S code already sets up a temporary map to higher addresses, so we can use INIT_VM_MIN_KERNEL_ADDRESS as in xen - increase the kernel map size to accomodate for bigger structures and more memory - adjust kernel max address and directmap limit * i386/i386at/biosmem.c: enable directmap check also on x86_64 * i386/include/mach/i386/vm_param.h: increase user virtual memory limit as it's not conflicting with the kernel's anymore * i386/intel/pmap.h: adjust lin2pdenum_cont() and INTEL_PTE_PFN to the new kernel map * x86_64/Makefrag.am: change KERNEL_MAP_BASE to be above 4G, and according to mcmodel=kernel. This will allow to use the full memory address space. Message-Id: <20230212172818.1511405-10-luca@orpolo.org>
* separate initialization of kernel and user PTP tablesLuca Dariz2023-02-123-20/+52
| | | | | | | | | | | | | * i386/i386/vm_param.h: temporariliy fix kernel upper address * i386/intel/pmap.c: split kernel and user L3 map initialization. For simplicity in handling the different configurations, on 32-bit (+PAE) the name PDPNUM_KERNEL is used in place of PDPNUM, while only on x86_64 the PDPNUM_USER and PDPNUM_KERNEL are treated differently. Also, change iterating over PTP tables in case the kernel map is not right after the user map. * i386/intel/pmap.h: define PDPNUM_USER and PDPNUM_KERNEL and move PDPSHIFT to simplify ifdefs. Message-Id: <20230212172818.1511405-9-luca@orpolo.org>
* extend data types to hold a 64-bit addressLuca Dariz2023-02-121-6/+6
| | | | | | | * i386/i386/trap.c: change from int to a proper type to hold a register value * x86_64/locore.S: use 64-bit register to avoid address truncation Message-Id: <20230212172818.1511405-8-luca@orpolo.org>
* add more explicit names for user space virtual space limitsLuca Dariz2023-02-125-19/+23
| | | | | | | | | | * i386/i386/vm_param.h: add VM_MAX/MIN_USER_ADDRESS to kernel headers. * i386/i386/db_interface.c * i386/i386/ldt.c * i386/i386/pcb.c * i386/intel/pmap.c * kern/task.c: replace VM_MAX/MIN_ADDRESS with VM_MAX/MIN_USER_ADDRESS Message-Id: <20230212172818.1511405-7-luca@orpolo.org>
* use L4 page table directly on x86_64 instead of short-circuiting to pdpbaseLuca Dariz2023-02-122-26/+78
| | | | | | | | | | | This is a preparation to run the kernel on high addresses, where the user vm region and the kernel vm region will use different L3 page tables. * i386/intel/pmap.c: on x86_64, retrieve the value of pdpbase from the L4 table, and add the pmap_pdp() helper (useful also for PAE). * i386/intel/pmap.h: remove pdpbase on x86_64. Message-Id: <20230212172818.1511405-6-luca@orpolo.org>
* factor out PAE-specific bootstrapLuca Dariz2023-02-121-32/+40
| | | | | * i386/intel/pmap.c: move it to pmap_bootstrap_pae() Message-Id: <20230212172818.1511405-5-luca@orpolo.org>
* factor out xen-specific bootstrapLuca Dariz2023-02-121-51/+56
| | | | | * i386/intel/pmap.c: move it to pmap_bootstrap_xen() Message-Id: <20230212172818.1511405-4-luca@orpolo.org>
* pmap: Fix warningSamuel Thibault2023-02-121-2/+3
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* prepare pmap helpers for full 64 bit memory mapLuca Dariz2023-02-121-5/+23
| | | | | | | * i386/intel/pmap.c: start walking the page table tree from the L4 table instead of the PDP table in pmap_pte() and pmap_pde(), preparing for the kernel to run on high addresses. Message-Id: <20230212172818.1511405-2-luca@orpolo.org>
* add L4 kmem cache for x86_64Luca Dariz2023-02-121-15/+19
| | | | | | | * i386/intel/pmap.c: allocate the L4 page table from a dedicate kmem cache instead of the generic kernel map. Also improve readability of nested ifdef's. Message-Id: <20230212170313.1501404-4-luca@orpolo.org>
* fix hardcoded physical addressLuca Dariz2023-02-121-1/+1
| | | | | | * i386/i386at/com.c use proper helper to convert physical to virtual address. Message-Id: <20230212170313.1501404-3-luca@orpolo.org>
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