import(life): ...

6 files changed, 128 insertions, 28 deletions

diff --git a/works/life/computer-organization-experiment/Makefile b/works/life/computer-organization-experiment/Makefile
index d44613c..1335118 100644
--- a/works/life/computer-organization-experiment/Makefile
+++ b/works/life/computer-organization-experiment/Makefile
@@ -1,4 +1,4 @@
-all: build/counter_4.o build/test_bench.o build/full_adder_1.o build/test_bench
+all: build/test_bench
 
 build:
 	mkdir -p build
@@ -9,10 +9,19 @@ build/counter_4.o: build counter_4.vhdl
 build/full_adder_1.o: build full_adder_1.vhdl
 	ghdl analyze --workdir=build -fsynopsys full_adder_1.vhdl
 
-build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o
+build/multiplexer_1_2.o: build multiplexer_1_2.vhdl
+	ghdl analyze --workdir=build -fsynopsys multiplexer_1_2.vhdl
+
+build/multiplexer_8_2.o: build multiplexer_8_2.vhdl
+	ghdl analyze --workdir=build -fsynopsys multiplexer_8_2.vhdl
+
+build/multiplexer_32_2.o: build multiplexer_32_2.vhdl
+	ghdl analyze --workdir=build -fsynopsys multiplexer_32_2.vhdl
+
+build/test_bench.o: build test_bench.vhdl build/counter_4.o build/full_adder_1.o build/multiplexer_1_2.o build/multiplexer_8_2.o build/multiplexer_32_2.o
 	ghdl analyze --workdir=build -fsynopsys test_bench.vhdl
 
-build/test_bench: build/counter_4.o build/full_adder_1.o build/test_bench.o
+build/test_bench: build/test_bench.o
 	ghdl elaborate --workdir=build -fsynopsys -o build/test_bench test_bench 
 
 .PHONY: all clean
diff --git a/works/life/computer-organization-experiment/hdl-prj.json b/works/life/computer-organization-experiment/hdl-prj.json
index 91428c1..1d997bb 100644
--- a/works/life/computer-organization-experiment/hdl-prj.json
+++ b/works/life/computer-organization-experiment/hdl-prj.json
@@ -17,6 +17,18 @@
         {
             "file": "test_bench.vhdl",
             "language": "vhdl"
+        },
+        {
+            "file": "multiplexer_1_2.vhdl",
+            "language": "vhdl"
+        },
+        {
+            "file": "multiplexer_8_2.vhdl",
+            "language": "vhdl"
+        },
+        {
+            "file": "multiplexer_32_2.vhdl",
+            "language": "vhdl"
         }
     ]
 }
\ No newline at end of file
diff --git a/works/life/computer-organization-experiment/multiplexer_1_2.vhdl b/works/life/computer-organization-experiment/multiplexer_1_2.vhdl
new file mode 100644
index 0000000..5f73d6a
--- /dev/null
+++ b/works/life/computer-organization-experiment/multiplexer_1_2.vhdl
@@ -0,0 +1,20 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity multiplexer_1_2 is
+  port (A0, A1, S : in std_logic; Y: out std_logic);
+end multiplexer_1_2;
+
+architecture behaviour of multiplexer_1_2 is
+begin
+  b: process is
+  begin
+    if S = '1' then
+      Y <= A1;
+    else
+      Y <= A0;
+    end if;
+    wait for 5 ns;
+  end process b;
+end behaviour;
diff --git a/works/life/computer-organization-experiment/multiplexer_32_2.vhdl b/works/life/computer-organization-experiment/multiplexer_32_2.vhdl
new file mode 100644
index 0000000..917e0e3
--- /dev/null
+++ b/works/life/computer-organization-experiment/multiplexer_32_2.vhdl
@@ -0,0 +1,20 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity multiplexer_32_2 is
+  port (A0, A1 : in std_logic_vector(31 downto 0); S : in std_logic; Y : out std_logic_vector(31 downto 0));
+end multiplexer_32_2;
+
+architecture behaviour of multiplexer_32_2 is
+begin
+  b: process is
+  begin
+    if S = '1' then
+      Y <= A1;
+    else
+      Y <= A0;
+    end if;
+    wait for 5 ns;
+  end process b;
+end behaviour;
diff --git a/works/life/computer-organization-experiment/multiplexer_8_2.vhdl b/works/life/computer-organization-experiment/multiplexer_8_2.vhdl
new file mode 100644
index 0000000..5fffbf4
--- /dev/null
+++ b/works/life/computer-organization-experiment/multiplexer_8_2.vhdl
@@ -0,0 +1,20 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity multiplexer_8_2 is
+  port (A0, A1 : in std_logic_vector(7 downto 0); S : in std_logic; Y : out std_logic_vector(7 downto 0));
+end multiplexer_8_2;
+
+architecture behaviour of multiplexer_8_2 is
+begin
+  b: process is
+  begin
+    if S = '1' then
+      Y <= A1;
+    else
+      Y <= A0;
+    end if;
+    wait for 5 ns;
+  end process b;
+end behaviour;
diff --git a/works/life/computer-organization-experiment/test_bench.vhdl b/works/life/computer-organization-experiment/test_bench.vhdl
index be15df9..756aa8d 100644
--- a/works/life/computer-organization-experiment/test_bench.vhdl
+++ b/works/life/computer-organization-experiment/test_bench.vhdl
@@ -9,20 +9,20 @@ architecture test_counter_4 of test_bench is
   signal CLK : STD_LOGIC;
   signal CQ: STD_LOGIC_VECTOR(3 DOWNTO 0);
 begin
-    counter: entity work.counter_4(behavior)
-        port map (CLK, CQ);
-    stimulus: process is
-    begin
-      for count_value in 0 to 2 ** 4 - 1 loop
-        if count_value mod 2 = 0 then
-          CLK <= '1';
-          wait for 5 ns;
-        else
-          CLK <= '0';
-          wait for 5 ns;
-        end if;
-      end loop;
-    end process stimulus;
+  counter: entity work.counter_4(behavior)
+      port map (CLK, CQ);
+  stimulus: process is
+  begin
+    for count_value in 0 to 2 ** 4 - 1 loop
+      if count_value mod 2 = 0 then
+        CLK <= '1';
+        wait for 5 ns;
+      else
+        CLK <= '0';
+        wait for 5 ns;
+      end if;
+    end loop;
+  end process stimulus;
 end architecture test_counter_4;
 
 
@@ -31,15 +31,34 @@ architecture test_full_adder_1 of test_bench is
   signal I: v3 := B"000";
   signal S, CO : STD_LOGIC;
 begin
-    adder: entity work.full_adder_1(behavior)
-        port map (I(2), I(1), I(0), S, CO);
-    stimulus: process is
-      variable ii : v3 := B"000";
-    begin
-      loop
-        ii := ii + 1;
-        I <= ii;
-        wait for 5 ns;
-      end loop;
-    end process stimulus;
+  adder: entity work.full_adder_1(behavior)
+      port map (I(2), I(1), I(0), S, CO);
+  stimulus: process is
+    variable ii : v3 := B"000";
+  begin
+    loop
+      ii := ii + 1;
+      I <= ii;
+      wait for 5 ns;
+    end loop;
+  end process stimulus;
 end architecture test_full_adder_1;
+
+architecture test_multiplexer_32_2 of test_bench is
+  signal A0: std_logic_vector(31 downto 0) := B"11111111111111111111111111111111";
+  signal A1: std_logic_vector(31 downto 0) := B"00000000000000000000000000000000";
+  signal S: std_logic;
+  signal Y: std_logic_vector(31 downto 0);
+begin
+  multiplexer: entity work.multiplexer_32_2(behaviour)
+      port map (A0, A1, S, Y);
+  stimulus: process is
+  begin
+    loop
+      S <= '0';
+      wait for 5 ns;
+      S <= '1';
+      wait for 5 ns;
+    end loop;
+  end process stimulus;
+end architecture test_multiplexer_32_2;